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i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 revision: v1.10 date: ?? ne 10 ? ? 01 ? ?? ne 10 ? ? 01 ?
rev. 1.10 ? ?? ne 10 ? ? 01 ? rev. 1.10 ? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi table of contents features ............................................................................................................ 6 cpu feat ? res ......................................................................................................................... 6 peripheral feat ? res ................................................................................................................. 6 general description ......................................................................................... 7 selection table ................................................................................................. 8 block diagram .................................................................................................. 8 pin assignment ................................................................................................ 9 pin description .............................................................................................. 12 absolute maximum ratings .......................................................................... 18 d.c. characteristics ....................................................................................... 18 a.c. characteristics ....................................................................................... 20 lvd & lvr electrical characteristics .......................................................... 21 power on reset (ac+dc) electrical characteristics .................................. 21 system architecture ...................................................................................... 22 clocking and pipelining ......................................................................................................... ?? program co ? nter ................................................................................................................... ?? stack ..................................................................................................................................... ? 4 arithmetic and logic unit C alu ........................................................................................... ? 4 flash program memory ................................................................................. 25 str ? ct ? re ................................................................................................................................ ? 5 special vectors ..................................................................................................................... ? 5 look- ? p table ........................................................................................................................ ? 6 table program example ........................................................................................................ ? 6 partial lock ........................................................................................................................... ? 7 in system programming C isp .............................................................................................. ? 8 flash memory read/write page size ................................................................................... ? 8 isp bootloader ...................................................................................................................... ? 0 flash program memory registers ........................................................................................ ? 0 in application program C iap ............................................................................................... ? 4 in circ ? it programming C icp ............................................................................................... ? 8 on-chip deb ? g s ? pport C ocds ......................................................................................... ? 8 ram data memory ......................................................................................... 39 str ? ct ? re ................................................................................................................................ ? 9 special function register description ........................................................ 43 indirect addressing registers C iar0 ? iar1 ......................................................................... 4 ? memory pointers C mp0 ? mp1 .............................................................................................. 4 ? bank pointer C bp ................................................................................................................. 44 acc ? m ? lator C acc ............................................................................................................... 45
rev. 1.10 ? ??ne 10? ?01? rev. 1.10 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi program co ? nter low register C pcl .................................................................................. 45 look- ? p table registers C tblp ? tbhp ? tblh ..................................................................... 45 stat ? s register C status .................................................................................................... 46 oscillator ........................................................................................................ 47 oscillator overview ............................................................................................................... 47 system clock confgurations ................................................................................................ 47 external crystal oscillator C hxt .......................................................................................... 48 internal pll freq ? ency generator ........................................................................................ 49 internal rc oscillator C hirc ............................................................................................... 51 internal ?? khz oscillator C lirc ........................................................................................... 51 s ? pplementary internal clocks ............................................................................................. 51 operating modes and system clocks ......................................................... 51 system clocks ...................................................................................................................... 51 system operation modes ...................................................................................................... 5 ? control register .................................................................................................................... 54 fast wake- ? p ........................................................................................................................ 55 operating mode switching and wake- ? p .............................................................................. 56 standby c ? rrent considerations ........................................................................................... 59 wake- ? p ................................................................................................................................ 60 programming considerations ................................................................................................ 60 watchdog timer ............................................................................................. 61 watchdog timer clock so ? rce .............................................................................................. 61 watchdog timer control register ......................................................................................... 61 watchdog timer operation ................................................................................................... 6 ? reset and initialisation .................................................................................. 63 reset overview ..................................................................................................................... 6 ? reset f ? nctions .................................................................................................................... 64 reset initial conditions ......................................................................................................... 68 input/output ports ......................................................................................... 78 p ? ll-high resistors ................................................................................................................ 80 port wake- ? p ........................................................................................................................ 8 ? port a wake- ? p polarity control register ............................................................................ 8 ? i/o port control registers ..................................................................................................... 84 port a ? port d power so ? rce control registers .................................................................. 85 i/o pin str ? ct ? res .................................................................................................................. 87 programming considerations ................................................................................................ 87 timer modules C tm ...................................................................................... 88 introd ? ction ........................................................................................................................... 88 tm operation ........................................................................................................................ 88 tm clock so ? rce ................................................................................................................... 89 tm interr ? pts ......................................................................................................................... 89 tm external pins ................................................................................................................... 89 tm inp ? t/o ? tp ? t pin control registers ................................................................................. 90 programming considerations ................................................................................................ 9 ?
rev. 1.10 4 ?? ne 10 ? ? 01 ? rev. 1.10 5 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi compact type tm ................................................................................................................. 94 compact tm operation ......................................................................................................... 95 compact type tm register description ................................................................................ 95 compact type tm operating modes .................................................................................... 99 compare match o ? tp ? t mode ............................................................................................... 99 timer/co ? nter mode ........................................................................................................... 101 pwm o ? tp ? t mode .............................................................................................................. 10 ? standard type tm C stm ............................................................................ 105 standard tm operation ....................................................................................................... 105 standard type tm register description ............................................................................. 106 standard type tm operating modes ................................................................................... 11 ? compare o ? tp ? t mode ......................................................................................................... 11 ? timer/co ? nter mode ............................................................................................................ 114 timer/co ? nter mode ............................................................................................................ 115 pwm o ? tp ? t mode ............................................................................................................... 115 single p ? lse mode ............................................................................................................... 118 capt ? re inp ? t mode ............................................................................................................ 1 ? 0 serial interface module C sim ..................................................................... 122 spi interface ....................................................................................................................... 1 ?? spi interface operation ....................................................................................................... 1 ?? spi registers ...................................................................................................................... 1 ?? spi comm ? nication ............................................................................................................ 1 ? 6 spi b ? s enable/disable ...................................................................................................... 1 ? 8 spi operation ...................................................................................................................... 1 ? 9 error detection .................................................................................................................... 1 ? 0 i ? c interface ........................................................................................................................ 1 ? 0 i ? c b ? s comm ? nication ...................................................................................................... 1 ? 5 i ? c b ? s start signal ............................................................................................................. 1 ? 6 i ? c b ? s slave address ........................................................................................................ 1 ? 6 i ? c b ? s read/write signal .................................................................................................. 1 ? 7 i ? c b ? s slave address acknowledge signal ....................................................................... 1 ? 7 i ? c b ? s data and acknowledge signal ............................................................................... 1 ? 7 i ? c time o ? t f ? nction ......................................................................................................... 1 ? 9 serial interface C spia ....................................................................................................... 1 ? 9 spia interface operation .................................................................................................... 140 spia registers .................................................................................................................... 141 spia communication .................................................................................. 143 spia b ? s enable/disable .................................................................................................... 145 spia operation ................................................................................................................... 146 error detection .................................................................................................................... 147 peripheral clock output .............................................................................. 148 peripheral clock operation ................................................................................................. 148 interrupts ...................................................................................................... 149 interr ? pt registers ............................................................................................................... 149
rev. 1.10 4 ??ne 10? ?01? rev. 1.10 5 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi interr ? pt operation .............................................................................................................. 15 ? external interr ? pt ................................................................................................................. 154 usb interr ? pt ...................................................................................................................... 155 serial interface mod ? le interr ? pts C sim interr ? pt .............................................................. 155 serial peripheral interface interr ? pt C spia interr ? pt .......................................................... 155 lvd interr ? pt ....................................................................................................................... 155 m ? lti-f ? nction interr ? pt ........................................................................................................ 155 tm interr ? pts ....................................................................................................................... 156 interr ? pt wake- ? p f ? nction ................................................................................................. 156 programming considerations .............................................................................................. 156 low voltage detector C lvd ....................................................................... 157 lvd register ....................................................................................................................... 157 lvd operation ..................................................................................................................... 158 usb interface ............................................................................................... 158 power plane ........................................................................................................................ 159 usb s ? spend wake-up remote wake-up ........................................................................ 159 usb interface operation ..................................................................................................... 160 usb interface registers ...................................................................................................... 161 confguration options ................................................................................. 178 application circuits ..................................................................................... 179 instruction set .............................................................................................. 180 introd ? ction ......................................................................................................................... 180 instr ? ction timing ................................................................................................................ 180 moving and transferring data ............................................................................................. 180 arithmetic operations .......................................................................................................... 180 logical and rotate operations ............................................................................................ 181 branches and control transfer ........................................................................................... 181 bit operations ..................................................................................................................... 181 table read operations ....................................................................................................... 181 other operations ................................................................................................................. 181 instr ? ction set s ? mmary ..................................................................................................... 18 ? instruction defnition ................................................................................... 184 package information ................................................................................... 193 ? 0-pin ssop (150mil) o ? tline dimensions ......................................................................... 194 ? 4-pin ssop (150mil) o ? tline dimensions ......................................................................... 195 ? 8-pin ssop (150mil) o ? tline dimensions ......................................................................... 196 saw type ? 0-pin (4mm 4 mm) qfn o ? tline dimensions .................................................. 197 48-pin lqfn (7mm 7mm) o ? tline dimensions .................................................................. 198
rev. 1.10 6 ?? ne 10 ? ? 01 ? rev. 1.10 7 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi features cpu features ? operating voltage : v dd (mcu) C f sys = 4mhz/6mhz: 2.2v~5.5v C f sys = 12mhz: 2.7v~5.5v v dd (usb mode) C f sys = 6mhz/12mhz: 3.3v~5.5v C f sys = 16mhz: 4.5v~5.5v ? up to 0.25s instruction cycle with 16mhz system clock at v dd = 5v ? power down and wake-up functions to reduce power consumption ? three oscillators: external crystal - hxt internal rc - hirc internal 32khz rc - lirc ? multi-mode operation: normal, slow, idle and sleep ? 2 compact type 10-bit timer module - ctm ? 1 standard type 10-bit timer module - stm ? 1 standard type 16-bit timer module - stm ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 12-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 4k16~16k16 ? ram data memory: 2568~7688 ? usb 2.0 full speed compatible ? up to 8 endpoints supported including endpoint 0 ? all endpoints except endpoint 0 can support interrupt and bulk transfer ? all endpoints except endpoint 0 can be confgured as 8, 16, 32, 64 bytes fifo size ? endpoint 0 support control transfer ? endpoint 0 has 8 byte fifo ? support 3.3v ldo and internal udp 1.5k ohm pull-up resistor ? internal 12mhz rc osc with 0.25% accuracy for all usb modes ? watchdog timer function ? up to 37 bidirectional i/o lines ? dual pin-shared external interrupts ? multiple timer modules for time measurement, input capture, compare match output or pwm output or single pulse output function ? serial interface modules with dual spi and i 2 c interfaces ? single serial spi interface ? low voltage reset function
rev. 1.10 6 ??ne 10? ?01? rev. 1.10 7 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? low voltage detect function ? wide range of available package types ? flash program memory can be re-programmed up to 1,000,000 times ? flash program memory data retenton > 10 years ? support in system programming function - isp ? partial lock function general description the HT68FB540, ht68fb550 and ht68fb560 are flash memory i/o with usb type 8-bit high performance risc archi tecture mi crocontroller s , designed for appl ications tha t int erface dire ctly to which require an usb interface. offering users the convenience of flash memory multi- programming features, these device s also include a wide range of functions and features. other memory includes an area of ram data memory. multiple and extremely fexible timer modules provide timing, pulse generation and pwm generation functions. communication with the outside world is catered for by including fully integrated spi, i 2 c and usb interface functions, three popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. the external interrupt can be triggered with falling edges or both falling and rising edges. a full choice of three oscillator functions are provided including two fully integrated system oscillator s which requires no external components for their implementation. the ability to operate and switch dyna mically bet ween a range of ope rating mode s using dif ferent cl ock source s give s users the ability to optimize microcontroller operation and minimize power consumption. the inclusion of fexible i/o programming features along with many other features ensure that the devices will fnd specifc excellent use in a wide range of application possibilities such as motor driving, industrial control, consumer products, subsystem controllers, etc. the devices are fully supported by the holtek range of fully functional development and programming tools, providing a means for fast and effcient product development cycles.
rev. 1.10 8 ?? ne 10 ? ? 01 ? rev. 1.10 9 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi selection table most features are common to all devices, the main feature distinguishing them are program memory capacity, i/o count, stack capacity and package types. the following table summarises the main features of each device. part no. vdd program memory data memory i/o ext. interrupt timer module sim (spi/i 2 c) spi stack package HT68FB540 ? . ? v~ 5.5v 4k 16 ? 56 8 17 ? 10-bit ctm ? 10-bit stm 1 16-bit stm 1 8 ? 0qfn ? 0/ ? 4ssop ht68fb550 ? . ? v~ 5.5v 8k 16 51 ? 8 ? 5 ? 10-bit ctm ? 10-bit stm 1 16-bit stm 1 8 ? 4/ ? 8ssop 48lqfp ht68fb560 ? . ? v~ 5.5v 16k 16 768 8 ? 7 ? 10-bit ctm ? 10-bit stm 1 16-bit stm 1 1 ? ? 4/ ? 8ssop 48lqfp block diagram
? ?? ? ? ? ? ? ? - ? ? ? ? ? ? ? ? ? ? ?? ???? ? ?? ? ?? ? ? ?? ? ?
rev. 1.10 8 ??ne 10? ?01? rev. 1.10 9 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi pin assignment HT68FB540 20 ssop -a pa 7/ int 0/ scsa pe 0/ vddio udn/ gpio 0 udp / gpio 1 v ?? o ubus / pe 1/ vdd hvdd pa 6/ tck 0/ scka pa 5/ sdia / tp 1_0 pa 4/ sdoa / tp 0_0 pa ?/ tck ? pa ?/ tp ?_1/ osc ? pa 1/ tp ?_1/ osc 1 pa 0/ tck 1/ ocdsda ?0 19 18 17 16 15 14 1? 1? 11 1 ? ? 4 5 6 7 8 9 10 pe ? vss res / ocdsck pb 0/ sdo / sda pb 1/ sdi / scl pb ?/ tck ?/ sck ht 68 fb 540 20 qfn -a 6 7 8 9 10 16171819?0 1 ? ? 4 5 15 14 1? 1? 11 udn/gpio0 udp / gpio 1 v ??o ubus / pe 1/ vdd hvdd pa6/tck0/scka pa 0/ tck 1/ ocdsda pa 1/ tp ?_1/ osc 1 pa ?/ tp ?_1/ osc ? pa7/int0/scsa pa ?/ tck ? res/ocdsck pe 0/ vddio pa5/sdia/tp1_0 pb0/sdo/sda pb1/sdi/scl pb?/tck?/sck ht 68 fb 540 pe ? vss pa4/sdoa/tp0_0 ?4 ?? ?? ?1 ?0 19 18 17 16 15 14 1? 1 ? ? 4 5 6 7 8 9 10 11 1? ht 68fb 540 24 ssop -a pb 0/ sdo / sda pb 6/ int 1/ tp ?_0 pa 0/ tck 1/ ocdsda pa 7/ int 0/ scsa pa 6/ tck 0/ scka pa 5/ sdia / tp 1_0 pa 4/ sdoa / tp 0_0 pa ?/ tck ? pa ?/ tp ?_1/ osc ? pa 1/ tp ?_1/ osc 1 pe 0/ vddio pb 5/ pck / tp ?_0 udn/ gpio 0 udp / gpio 1 v ?? o ubus / pe 1/ vdd hvdd pe ? vss res / ocdsck pb 1/ sdi / scl pb 4/ tp 0_1 pb ?/ scs / tp 1_1 pb ?/ tck ?/ sck
rev. 1.10 10 ?? ne 10 ? ? 01 ? rev. 1.10 11 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ht68fb550 ht 68 fb 550 28 ssop -a ?8 ?7 ?6 ?5 ?4 ?? ?? ?1 ?0 19 18 17 16 15 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 pd ? pd ? pd 1 pd 0 pb 0/ sdo / sda pb 1/ sdi / scl pa 7/ int 0/ scsa pe 0/ vddio udn / gpio 0 udp / gpio 1 v ??o ubus / pe 1/ vdd hvdd pe ? vss res / ocdsck pa 6/ tck 0/ scka pa 5/ sdia / tp 1_0 pa 4/ sdoa / tp 0_0 pa ?/ tck ? pa ?/ tp ?_1/ osc ? pa 1/ tp ?_1/ osc 1 pa 0/ tck 1/ ocdsda pb 6/ int 1/ tp ?_0 pb ?/ tck ?/ sck pb 5/ pck / tp ?_0 pb 4/ tp 0_1 pb ?/ scs / tp 1_1 ?4 ?? ?? ?1 ?0 19 18 17 16 15 14 1? 1 ? ? 4 5 6 7 8 9 10 11 1? ht 68 fb 550 24 ssop -a pb 0/ sdo / sda pb 1/ sdi / scl pa 7/ int 0/ scsa pa 6/ tck 0/ scka pa 5/ sdia / tp 1_0 pa 4/ sdoa / tp 0_0 pa ?/ tck ? pa ?/ tp ?_1/ osc ? pa 1/ tp ?_1/ osc 1 pa 0/ tck 1/ ocdsda pe 0/ vddio pb 6/ int 1/ tp ?_0 udn/ gpio 0 udp / gpio 1 v ?? o ubus / pe 1/ vdd hvdd pe ? vss res / ocdsck pb ?/ tck ?/ sck pb 5/ pck / tp ?_0 pb 4/ tp 0_1 pb ?/ scs / tp 1_1 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 1516 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 45 464748 ?7?8?940414?4?44 ht 68 fb 550 48 lqfp -a nc nc nc udn / gpio 0 udp / gpio 1 v ??o ubus / pe 1/ vdd hvdd pe ? vss nc res / ocdsck pd 4 pa ?/ tp ?_1/ osc ? pa 1/ tp ?_1/ osc 1 pa 0/ tck 1/ ocdsda pd ? pd ? pd1 pd0 pa4/sdoa/tp0_0 pd 7 pd 6 pd 5 nc pb5/pck/tp?_0 nc nc pa7/int0/scsa pa6/tck0/scka pa5/sdia/tp1_0 nc nc nc nc nc nc nc pb0/sdo/sda pb1/sdi/scl pb?/tck?/sck pb?/scs/tp1_1 pb4/tp0_1 pb 6/ int 1/ tp ?_0 nc nc pa?/tck? pe 0/ vddio
rev. 1.10 10 ??ne 10? ?01? rev. 1.10 11 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ht68fb560 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 1516 17 18 19 ?0 ?1 ?? ?? ?4 ?5 ?6 ?7 ?8 ?9 ?0 ?1 ?? ?? ?4 ?5 ?6 45 464748 ?7?8?940414?4?44 ht 68fb 560 48 lqfp -a pe4 pe? pc 7 udn / gpio 0 udp / gpio 1 v ??o ubus / pe 1/ vdd hvdd pe ? vss pe 5 res / ocdsck pd 4 pa ?/ tp ?_1/ osc ? pa 1/ tp ?_1/ osc 1 pa 0/ tck 1/ ocdsda pd ? pd ? pd1 pd0 pa4/sdoa/tp0_0 pd 7 pd 6 pd 5 pb 7 pb5/pck/tp?_0 nc nc pa7/int0/scsa pa6/tck0/scka pa5/sdia/tp1_0 pc1 pc0 pc? pc? pc4 pc5 pc6 pb0/sdo/sda pb1/sdi/scl pb?/tck?/sck pb?/scs/tp1_1 pb4/tp0_1 ht 68fb 560 28 ssop -a ?8 ?7 ?6 ?5 ?4 ?? ?? ?1 ?0 19 18 17 16 15 1 ? ? 4 5 6 7 8 9 10 11 1? 1? 14 pd ? pd ? pd 1 pd 0 pb 0/ sdo / sda pb 1/ sdi / scl pa 7/ int 0/ scsa pe 0/ vddio udn/ gpio 0 udp / gpio 1 v ?? o ubus / pe 1/ vdd hvdd pe ? vss res / ocdsck pa 6/ tck 0/ scka pa 5/ sdia / tp 1_0 pa 4/ sdoa / tp 0_0 pa ?/ tck ? pa ?/ tp ?_1/ osc ? pa 1/ tp ?_1/ osc 1 pa 0/ tck 1/ ocdsda pb 6/ int 1/ tp ?_0 pb ?/ tck ?/ sck pb 5/ pck / tp ?_0 pb 4/ tp 0_1 pb ?/ scs / tp 1_1 pb 6/ int 1/ tp ?_0 nc nc ?4 ?? ?? ?1 ?0 19 18 17 16 15 14 1? 1 ? ? 4 5 6 7 8 9 10 11 1? ht 68 fb 560 24 ssop -a pb 0/ sdo / sda pb 1/ sdi / scl pa 7/ int 0/ scsa pa 6/ tck 0/ scka pa 5/ sdia / tp 1_0 pa 4/ sdoa / tp 0_0 pa ?/ tck ? pa ?/ tp ?_1/ osc ? pa 1/ tp ?_1/ osc 1 pa 0/ tck 1/ ocdsda pe 0/ vddio pb 6/ int 1/ tp ?_0 udn/ gpio 0 udp / gpio 1 v ?? o ubus / pe 1/ vdd hvdd pe ? vss res / ocdsck pb ?/ tck ?/ sck pb 5/ pck / tp ?_0 pb 4/ tp 0_1 pb ?/ scs / tp 1_1 pa?/tck? pe 0/ vddio
rev. 1.10 1 ? ?? ne 10 ? ? 01 ? rev. 1.10 1? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi pin description the pins on these devices can be referenced by their port name, e.g. pa.0, pa.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the serial port pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. HT68FB540 pin name function opt i/t o/t description pa0/tck1/ ocdsda pa0 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck1 st tm1 inp ? t ocdsda st cmos deb ? g data i/o in on-chip deb ? g s ? pport mode. pa1/tp ? _1/osc1 pa1 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tp ? _1 tmpc1 st cmos tm ? i/o osc1 hxt hxt pin pa ? /tp ? _1/osc ? pa ? papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tp ? _1 tmpc1 st cmos tm ? i/o osc ? hxt hxt pin pa ? /tck ? pa ? papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck ? st tm ? inp ? t pa4/sdoa/tp0_0 pa4 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdoa cmos spia data o ? tp ? t tp0_0 tmpc0 st cmos tm0 i/o pa5/sdia/tp1_0 pa5 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdia st spia data inp ? t tp1_0 tmpc0 st cmos tm1 i/o pa6/tck0/scka pa6 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck0 st tm0 inp ? t scka st nmos spia serial clock pa7/int0/ scsa pa7 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. int0 st external interr ? pt 0 scsa st cmos spia slave select pb0/sdo/sda pb0 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdo cmos spi data o ? tp ? t sda st nmos i ? c data pb1/sdi/scl pb1 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdi st spi data inp ? t scl st nmos i ? c clock
rev. 1.10 1? ??ne 10? ?01? rev. 1.10 1 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi pin name function opt i/t o/t description pb ? /tck ? /sck pb ? pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck ? tmpc1 st tm ? inp ? t sck st cmos spi serial clock pb ? / scs/tp1_1 pb ? pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. scs st cmos spi slave select tp1_1 tmpc0 st cmos tm1 i/o pb4/tp0_1 pb4 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tp0_1 tmpc0 st cmos tm0 i/o pb5/pck/tp ? _0 pb5 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. pck cmos peripheral o ? tp ? t clock tp ? _0 tmpc1 st cmos tm ? i/o pb6/int1/tp ? _0 pb6 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. int1 st external interr ? pt 1 tp ? _0 tmpc1 st cmos tm ? i/o pe0/vddio pe0 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. vddio pwr pa external power inp ? t vdd/pe1/ubus vdd pwr power s ? pply pe1 st general p ? rpose i/o ? inp ? t pin ubus pwr usb sie vdd pe ? pe ? pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. res/ocdsck res st reset inp ? t ocdsck st deb ? g clock inp ? t in on-chip deb ? g s ? pport mode. udn/gpio0 udn st cmos usb udn line gpio0 st cmos general p ? rpose i/o udp/gpio1 udp st cmos usb udp line gpio1 st cmos general p ? rpose i/o vss vss pwr gro ? nd v ?? o v ?? o pwr ? . ? v reg ? lator o ? tp ? t hvdd hvdd pwr hirc oscillator positive power s ? pply. note: i/t: input type o/t: output type opt: optional by confguration option (co) or register option pwr: power co: confguration option st: schmitt trigger input cmos: cmos output hxt: high frequency crystal oscillator where devices exist in more than one package type the table refects the situation for the package with the largest number of pins. for this reason not all pins described in the table may exist on all package types.
rev. 1.10 14 ?? ne 10 ? ? 01 ? rev. 1.10 15 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ht68fb550 pin name function opt i/t o/t description pa0/tck1/ ocdsda pa0 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck1 st tm1 inp ? t ocdsda st cmos deb ? g data i/o in on-chip deb ? g s ? pport mode. pa1/tp ? _1/osc1 pa1 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p tp ? _1 tmpc1 st cmos tm ? i/o osc1 hxt hxt pin pa ? /tp ? _1/osc ? pa ? papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tp ? _1 tmpc1 st cmos tm ? i/o osc ? hxt hxt pin pa ? /tck ? pa ? papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck ? st tm ? inp ? t pa4/sdoa/tp0_0 pa4 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdoa cmos spia data o ? tp ? t tp0_0 tmpc0 st cmos tm0 i/o pa5/sdia/tp1_0 pa5 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdia st spia data inp ? t tp1_0 tmpc0 st cmos tm1 i/o pa6/tck0/scka pa6 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck0 st tm0 inp ? t scka st nmos spia serial clock pa7/int0/ scsa pa7 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. int0 st external interr ? pt 0 scsa st cmos spia slave select pb0/sdo/sda pb0 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdo cmos spi data o ? tp ? t sda st nmos i ? c data pb1/sdi/scl pb1 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdi st spi data inp ? t scl st nmos i ? c clock pb ? /tck ? /sck pb ? pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck ? tmpc1 st tm ? inp ? t sck st cmos spi serial clock
rev. 1.10 14 ??ne 10? ?01? rev. 1.10 15 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi pin name function opt i/t o/t description pb ? / scs/tp1_1 pb ? pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. scs st cmos spi slave select tp1_1 tmpc0 st cmos tm1 i/o pb4/tp0_1 pb4 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tp0_1 tmpc0 st cmos tm0 i/o pb5/pck/tp ? _0 pb5 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. pck cmos peripheral o ? tp ? t clock. tp ? _0 tmpc1 st cmos tm ? i/o pb6/ int1/ tp ? _0 pb6 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. int1 st external interr ? pt 1 tp ? _0 tmpc1 st cmos tm ? i/o pd0~pd7 pd0~pd7 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. pe0/vddio pe0 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. vddio pwr pa ? pd4~pd7 external power inp ? t. vdd/pe1/ubus vdd pwr power s ? pply pe1 st general p ? rpose i/o ? inp ? t pin ubus pwr usb sie vdd pe ? pe ? pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. res/ocdsck res st reset inp ? t ocdsck st deb ? g clock inp ? t in on-chip deb ? g s ? pport mode udn/gpio0 udn st cmos usb udn line. gpio0 st cmos general p ? rpose i/o udp/gpio1 udp st cmos usb udp line gpio1 st cmos general p ? rpose i/o vss vss pwr gro ? nd v ?? o v ?? o pwr ? . ? v reg ? lator o ? tp ? t hvdd hvdd pwr hirc oscillator positive power s ? pply. note: i/t: input type o/t: output type opt: optional by confguration option (co) or register option pwr: power co: confguration option st: schmitt trigger input cmos: cmos output hxt: high frequency crystal oscillator where devices exist in more than one package type the table refects the situation for the package with the largest number of pins. for this reason not all pins described in the table may exist on all package types.
rev. 1.10 16 ?? ne 10 ? ? 01 ? rev. 1.10 17 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ht68fb560 pin name function opt i/t o/t description pa0/tck1/ ocdsda pa0 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck1 st tm1 inp ? t ocdsda st cmos deb ? g data i/o in on-chip deb ? g s ? pport mode pa1/tp ? _1/osc1 pa1 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tp ? _1 tmpc1 st cmos tm ? i/o osc1 hxt hxt pin pa ? /tp ? _1/osc ? pa ? papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tp ? _1 tmpc1 st cmos tm ? i/o osc ? hxt hxt pin pa ? /tck ? pa ? papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck ? st tm ? inp ? t pa4/sdoa/tp0_0 pa4 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdoa cmos spia data o ? tp ? t tp0_0 tmpc0 st cmos tm0 i/o pa5/sdia/tp1_0 pa5 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdia st spia data inp ? t tp1_0 tmpc0 st cmos tm1 i/o pa6/tck0/scka pa6 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck0 st tm0 inp ? t scka st nmos spia serial clock pa7/int0/ scsa pa7 papu pawu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. int0 st external interr ? pt 0 scsa st cmos spia slave select pb0/sdo/sda pb0 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdo cmos spi data o ? tp ? t sda st nmos i ? c data pb1/sdi/scl pb1 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. sdi st spi data inp ? t scl st nmos i ? c clock pb ? /tck ? /sck pb ? pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tck ? tmpc1 st tm ? inp ? t sck st cmos spi serial clock
rev. 1.10 16 ??ne 10? ?01? rev. 1.10 17 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi pin name function opt i/t o/t description pb ? / scs/tp1_1 pb ? pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. scs st cmos spi slave select tp1_1 tmpc0 st cmos tm1 i/o pb4/tp0_1 pb4 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. tp0_1 tmpc0 st cmos tm0 i/o pb5/pck/tp ? _0 pb5 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. pck cmos peripheral o ? tp ? t clock tp ? _0 tmpc1 st cmos tm ? i/o pb6/int1/tp ? _0 pb6 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. int1 st external interr ? pt 1 tp ? _0 tmpc1 st cmos tm ? i/o pb7 pb7 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. pc0~pc7 pc0~pc7 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. pd0~pd7 pd0~pd7 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. pe0/vddio pe0 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. vddio pwr pa ? pd4~pd7 external power inp ? t vdd/pe1/ubus vdd pwr power s ? pply. pe1 st general p ? rpose i/o ? inp ? t pin ubus pwr usb sie vdd pe ? ~pe5 pe ? ~pe5 pxpu pxwu st cmos general p ? rpose i/o. register enabled p ? ll- ? p and wake- ? p. res/ocdsck res st reset inp ? t ocdsck st deb ? g clock inp ? t in on-chip deb ? g s ? pport mode udn/gpio0 udn st cmos usb udn line gpio0 st cmos general p ? rpose i/o. udp/gpio1 udp st cmos usb udp line gpio1 st cmos general p ? rpose i/o. vss vss pwr gro ? nd v ?? o v ?? o pwr ? . ? v reg ? lator o ? tp ? t hvdd hvdd pwr hirc oscillator positive power s ? pply. note: i/t: input type o/t: output type opt: optional by confguration option (co) or register option pwr: power co: confguration option st: schmitt trigger input cmos: cmos output hxt: high frequency crystal oscillator where devices exist in more than one package type the table refects the situation for the package with the largest number of pins. for this reason not all pins described in the table may exist on all package types.
rev. 1.10 18 ?? ne 10 ? ? 01 ? rev. 1.10 19 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi note: these are stre ss rat ings only . stre sses exc eeding the range spec ifed under "absolut e maxi mum rat ings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the spec ification is not im plied and prol onged expo sure to ext reme cond itions ma y af fect device reliability. d.c. characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 operating voltage (crystal osc) f sys =4mhz ? . ? 5.5 v f sys =6mhz ? . ? 5.5 v f sys =8mhz ? . ? 5.5 v f sys =1 ? mhz ? .7 5.5 v f sys =16mhz 4.5 5.5 v v dd ? operating voltage (high freq ? ency internal rc osc) f sys =1 ? mhz ? .7 5.5 v i dd1 operating c ? rrent (crystal osc ? f sys =f h ? f s =f lirc ) ? v no load ? f h =4mhz ? wdt enable 0.8 1.5 ma 5v 1.8 4.0 ma ? v no load ? f h =6mhz ? wdt enable 1.0 ? .0 ma 5v ? .5 5.0 ma ? v no load ? f h =8mhz ? wdt enable 1. ? ? .0 ma 5v ? .0 5.5 ma ? v no load ? f h =1 ? mhz ? wdt enable ? .0 4.0 ma 5v 4.0 7.0 ma i dd ? operating c ? rrent (hirc osc ? f sys =f h ? f s =f lirc ) ? v no load ? f h =1 ? mhz ? wdt enable ? .0 4.0 ma 5v 4.0 7.0 ma i dd ? operating c ? rrent (lirc osc ? f sys =f l =f lirc ? f s =f lirc ) ? v no load ? adc off ? f lirc = ?? khz ? wdt enable ? lvr enable 40 80 5v 70 150 i dd4 operating c ? rrent (hirc osc ? f sys =f h ? f s =f lirc ) ? v no load ? f h =1 ? mhz ? wdt enable ? usb enable ? pll on ? v ?? o on 5.5 10.0 ma 5v 11 16 ma i dd5 operating c ? rrent (crystal osc ? f sys =f h ? f s =f lirc ) 5v no load ? f h =6mhz ? wdt enable ? usb enable ? pll on ? v ?? o on 10 15 ma 5v no load ? f h =1 ? mhz ? wdt enable ? usb enable ? pll on ? v ?? o on 11 16 ma 5v no load ? f h =16mhz ? wdt enable ? usb enable ? pll on ? v ?? o on 1 ? 17 ma absolute maximum ratings supply voltage ........................ v ss -0.3v to v ss +6.0v input voltage ........................... v ss -0.3v to v dd +0.3v i ol total ............................................................. 150ma total power dissipation .................................... 500mv storage temperature .......................... -50c to 125c operating temperature ........................ -40c to 85c i oh total ........................................................... -100ma
rev. 1.10 18 ??ne 10? ?01? rev. 1.10 19 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi symbol parameter test conditions min. typ. max. unit v dd conditions i stb1 standby c ? rrent (idle 1) (crystal or hirc osc ? f sys =f h ? f s =f lirc ) ? v no load ? system halt ? wdt enable ? oscillator on (fsyson=1) 0.8 1.5 ma 5v 1.5 ? .0 ma i stb ? standby c ? rrent (idle 0) (crystal or hirc osc ? f sys =off ? f s =f lirc ) ? v no load ? system halt ? wdt enable ? oscillator off (fsyson=0) 1.5 ? .0 a 5v ? .0 6.0 a i stb ? standby c ? rrent (idle 0) (lirc osc ? f sys =off ? f s =f lirc ) ? v no load ? system halt ? wdt enable 1.5 ? .0 a 5v ? .0 6.0 a i stb4 standby c ? rrent (sleep 0) (crystal or hirc osc ? f sys =off ? f s =f lirc ) ? v no load ? system halt ? wdt disable 0.1 1.0 a 5v 0. ? ? .0 a i stb5 standby c ? rrent (sleep 0) (crystal or hirc osc ? f sys =off ? f s =f lirc ) no load ? system halt ? wdt disable ? lvr enable and lvden=1 60 90 a i sus1 s ? spend c ? rrent (sleep 0) (crystal or hirc osc ? f sys =off ? f s =f lirc ) 5v no load ? system halt ? wdt disable ? usb transceiver ? ? . ? v reg ? lator on and clr s ? spend ? (ucc.4) ? 60 4 ? 0 a i sus ? s ? spend c ? rrent (sleep 0) (crystal or hirc osc ? f sys =off ? f s =f lirc ) 5v no load ? system halt ? wdt disable ? usb transceiver ? ? . ? v reg ? lator on and set s ? spend ? (ucc.4) ? 40 ?? 0 a v il1 inp ? t low voltage for i/o ports ? tck and int 0 0. ? v dd v v ih1 inp ? t high voltage for i/o ports ? tck and int 0.8v dd v dd v v il ? inp ? t low voltage ( res) 0 0.4v dd v v ih ? inp ? t high voltage ( res) 0.9v dd v dd v i ol i/o port sink c ? rrent ? v v ol =0.1v dd 4 8 ma 5v v ol =0.1v dd 10 ? 0 ma i oh i/o port ? so ? rce c ? rrent ? v v oh =0.9v dd - ? -4 ma 5v v oh =0.9v dd -5 -10 ma v v ?? o ? . ? v reg ? lator o ? tp ? t 5v i v ?? o =70ma ? .0 ? . ? ? .6 v r udp p ? ll-high resistance of udp to v ?? o ? . ? v -5% 1.5 +5% k r ph p ? ll-high resistance of i/o ports ? v ? 0 60 100 k 5v 10 ? 0 50 k r pl p ? ll-low resistance of ubus pin 5v susp ? =1 ? rubus=0 0.5 1 1.5 m
rev. 1.10 ? 0 ?? ne 10 ? ? 01 ? rev. 1.10 ?1 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi a.c. characteristics ta= 25c symbol parameter v dd condition min. typ. max. unit f sys1 system clock (crystal osc) ? . ? ~5.5v ? 4 mhz ? . ? ~5.5v ? 6 mhz ? . ? ~5.5v ? 8 mhz ? .7~5.5v ? 1 ? mhz 4.5~5.5v ? 16 mhz f sys ? system clock (hirc osc) ? . ? ~5.5v non-usb mode ? ta= ? 5 c - ? % 1 ? + ? % mhz ? .0~5.5v non-usb mode ? ta= -40~85 c -6% 1 ? +6% mhz ? . ? ~5.5v non-usb mode ? ta=-40~85 c -10% 1 ? +10% mhz ? . ? ~5.5v usb mode -0. ? 5% 1 ? +0. ? 5% mhz f lirc system clock ( ?? k rc) 5v ta= ? 5 c -10% ?? +10% khz ? . ? ~5.5v ta= -40c to 85c -50% ?? +60% khz f timer timer i/p freq ? ency (tmr) ? . ? ~5.5v ? 8 mhz ? .7~5.5v ? 1 ? mhz 4.5~5.5v ? 16 mhz t bgs vbg t ? rn on stable time 10 ms t timer tckn inp ? t pin minim ? m p ? lse width 0. ? v t res external reset minim ? m low p ? lse width 10 v t int interr ? pt minim ? m p ? lse width 10 v t sst system start- ? p timer period (wake- ? p from halt ? f sys off at halt state ? slow mode normal mode) f sys =hxt (slow mode nor- mal mode (hxt)) 10 ? 4 t sys f sys =hxt (wake- ? p from halt ? f sys off at halt state) 10 ? 4 t sys f sys =hirc 10 ? 4 t sys f sys =lirc ? t sys system start- ? p timer period (wake- ? p from halt ? f sys on at halt state) ? t sys system start- ? p timer period (reset) 10 ? 4 t sys t rstd system reset delay time (power on reset) ? 5 50 100 ms system reset delay time (any reset except power on reset) 8. ? 16.7 ?? . ? ms
rev. 1.10 ?0 ??ne 10? ?01? rev. 1.10 ? 1 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi lvd & lvr electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr1 low voltage reset voltage lvr enable ? ? .1v option -5% typ. ? .1 +5% typ. v v lvr ? lvr enable ? ? .55v option ? .55 v v lvr ? lvr enable ? ? .15v option ? .15 v v lvr4 lvr enable ? ? .8v option ? .8 v v lvd1 low voltage detector voltage lvden=1 ? v lvd = ? .0v -5% typ. ? .0 +5% typ. v v lvd ? lvden=1 ? v lvd = ? . ? v ? . ? v v lvd ? lvden=1 ? v lvd = ? .4v ? .4 v v lvd4 lvden=1 ? v lvd = ? .7v ? .7 v v lvd5 lvden=1 ? v lvd = ? .0v ? .0 v v lvd6 lvden=1 ? v lvd = ? . ? v ? . ? v v lvd7 lvden=1 ? v lvd = ? .6v ? .6 v v lvd8 lvden=1 ? v lvd =4.0v 4.0 v i lvd additional power cons ? mption if lvd/lvr is used ? v lvd disable lvd enable (lvr enable) ? 0 45 5v 60 90 t lvr low voltage width to reset 1 ? 0 ? 40 480 v t lvd low voltage width to interr ? pt ? 0 45 90 v t sreset software reset width to reset 45 90 1 ? 0 v t lvds lvdo stable time for lvr enable ? lvd off on 15 v power on reset (ac+dc) electrical characteristics ta= 25c symbol parameter vdd condition min. typ. max. unit v por v dd start voltage to ens ? re power-on reset 100 mv rr vdd v dd rise rate to ens ? re power-on reset 0.0 ? 5 v/ms t por minim ? m time for v dd stays at v por to ens ? re power-on reset 1 ms
rev. 1.10 ?? ?? ne 10 ? ? 01 ? rev. 1.10 ?? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining sche me is im plemented in such a way tha t inst ruction fet ching and inst ruction execution are overla pped, hence inst ructions are ef fectively exec uted in one cycl e, wit h the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cyc les, th e pipe lining stru cture of th e mi crocontroller ensu res th at in structions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obta in the ac tual jum p or ca ll addre ss and the n anot her cyc le to ac tually exe cute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ?? system clocking and pipelining
rev. 1.10 ?? ??ne 10? ?01? rev. 1.10 ?? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program exe cution, the progra m count er is used to kee p tra ck of the addre ss of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed exc ept for inst ructions, such as "jmp" or "call " tha t dem and a jum p to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine ca ll, int errupt or reset , et c., the mi crocontroller ma nages program cont rol by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register HT68FB540 pc11~pc8 pcl7~pcl0 ht68fb550 pc1 ? ~pc8 ht68fb560 pc1 ? ~pc8 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, which is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.10 ? 4 ?? ne 10 ? ? 01 ? rev. 1.10 ?5 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has mu ltiple le vels de pending up on th e de vice an d is ne ither pa rt of th e da ta no r pa rt of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
device stack levels HT68FB540/ht68fb550 8 ht68fb560 1 ? arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.10 ?4 ??ne 10? ?01? rev. 1.10 ? 5 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large numbe r of ti mes, al lowing the user the conve nience of code modi fication on the sam e device. by using the appropriate programming tools, this flash device offers users the fexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 4kx16 bits to 16kx16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. device capacity banks HT68FB540 4k 16 0 ht68fb550 8k 16 0 ht68fb560 16k 16 0 ? 1 the ht68fb560 has its program memory divided into two banks, bank 0 and bank 1. the required bank is selected using bit 5 of the bp register . special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.

program memory structure
rev. 1.10 ? 6 ?? ne 10 ? ? 01 ? rev. 1.10 ?7 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up th e ta ble po inter, th e ta ble da ta ca n be re trieved fr om th e pro gram mem ory usi ng the "tabrd[m]" or "tabrdl[m]" instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory re gister [m ] as spe cified in th e in struction. th e hi gher or der ta ble da ta by te fr om the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as "0". the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is"1f00h" which refers to the start address of the la st pa ge wit hin th e 8k pro gram mem ory of th e ht6 8fb550. th e ta ble po inter is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "1f06h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.10 ?6 ??ne 10? ?01? rev. 1.10 ? 7 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi partial lock the fash program partial lock function is used to protect a block of program m emory. the fash program memory is divi ded int o seve ral bloc ks ac cording to the prog ram size. each bloc k siz e is assigned by 51 2 wor ds. th e pa rtial lo ck fu nction is enabled by the partial lo ck co nfiguration option s in the development to ol. if th e sel ected pa rtial lo ck c onfiguration op tion is sel ected , the corresponding partial lock function will be enabled and this block of program memory is unable to be accessed . any read operations will result in a value of "0000h". in this way, the user can select which block of the fash memory is to be protect ed. precautions should be taken when using the look-up table function in any locked block s . the look- up table pointer is implemented by the tblp and tbhp registers. when the table pointer is setup to point to an address in an unlocked block, the table read instruction functions normally however when the pointer points to a locked block, there are two conditions : ? if the table read instruction and the data table are located in the same block, then the table read instruction, tabrd[m], is valid. ? if the table read instruction and the data table are located in different block s , then the table read instruction is invalid. the read out data will be "0000h". the following ex ample il lustrates th e ba sic op eration of th e pa rtial lo ck fu nction using the HT68FB540 as an example. if the last block is locked and if the table pointer address is setup to point to the last block , and if the table read instruction is executed in the last block, the data read back is valid. if the last block is locked, but the table pointer address points to the last page in other block s , then when the table read instruction is executed, the read out data will be "0000h".

table read from different block the above example has the following setup: ? enable the last page partial lock function via the confguration option in the development tool. ? write data "0f00h" to the table pointer registers, tbhp and tblp. ? table read instruction not located in locked block. ? action: table read is invalid C data read back as 000h.
rev. 1.10 ? 8 ?? ne 10 ? ? 01 ? rev. 1.10 ?9 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

table read from same block the above example has the following setup: ? enable the last page partial lock function via the confguration option in the development tool. ? write data "0f00h" to the table pointer registers, tbhp and tblp. ? table read instruction is located in locked block. ? action: table read instruction is valid. in system programming C isp the provision of fla sh ty pe pro gram mem ory pr ovides th e use r wit h a me ans of co nvenient an d easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-system using a two-line usb interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the program memory can be programmed serially in-system using the usb interface, namely using the udn and udp pins. the power is supplied by the ubus pin. the technical details regarding the in-system programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. the flash program memory read/ write function is implemented using a series of registers . flash memory read/write page size there are two page sizes, 32 words or 64 words, assigned for various flash memory size. when the flash memory, larger than 8k bytes, is selected, the 64 word page size is assigned per page and buffer. otherwise, the page and buffer size are assigned as 32 words. the following diagram illustrates the read/write page and buffer assignment. the write buffer is controlled by the clwb bit in the frcr register. the clwb bit can be set high to enable the clear write buffer procedure, as the procedure is fnished, this bit will be cleared to low by hardware.
rev. 1.10 ?8 ??ne 10? ?01? rev. 1.10 ? 9 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi the write buffer is flled when the fwen bit is set to high, when this bit is set high, the data in the write buffer will be written to the flash rom, the fwt bit is used to indicate the writing procedure. setting this bit high and check if the write procedure is fnished, this bit will be cleared by hardware. the read byte can be assigned by the address. the frden is used to enable the read function and the frd is used to indicate the reading procedure. when the reading procedure is fnished, this bit will be cleared by hardware. device page size (words) write buffer (words) HT68FB540 (4k 16) ?? ?? ht68fb550 (8k 16) ?? ?? ht68fb560 (16k 16) 64 64 write b?ffer clwb flash memory farh farl fd 0h fd 0l write one word to fd0l/fd0h flash memory farh farl fd 0h fd 0l read one word to fd0l/fd0h note:1. writing a data into high byte, which means the h/l data is written into write buffer , will cause the flash memory address increased by one automatically and the new address will be loaded to the farh and farl regi sters. howeve r, the user ca n al so fil l the new ad dress by fil ling the data into farh and farl registers in the same page, then the data will be written into the corresponding address. 2. if the address already reached the boundary of the fash memory, such as 11 111b of the 32 words or 111111b of th e 64 wor ds. at th is mo ment, th e ad dress wil l not be in creased an d th e ad dress will stop at the last address of that page and the writing data is invalid. 3. at this point, the user has to set a new address again to fll a new data. 4. if the data is writ ing using the writ e buffe r, the writ e buffer will be cl eared by hardware automatically after the write procedure is ready in 2ms. 5. first time use the write buffer or renew the data in the write buffer , the user can use to clear buffer bit (clwb) to clear write buffer.
rev. 1.10 ? 0 ?? ne 10 ? ? 01 ? rev. 1.10 ?1 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi isp bootloader the devices provide the isp bootloader function to upgrade the software in the flash memory. the user can select to use the isp bootloader application software provided by holtek ide tool or to create his own bootloader software. when the holtek bootloader software is selected, that will occupy 0.5k words area in the flash memory. the accopanying diagram illustrates the flash memory structure with holtek bootloader software. ht 68 fb 540 bank 1 last page ht 68 fb 5 50 ht 68 fb 5 60 0000 h 0d 00 h 0 dffh last page bank 0 bootloader bootloader bootloader 0000 h 1d 00 h 1 dffh 0000 h 1 fffh last page ?d 00 h ? dffh flash program memory registers there are two ad dress re gisters, fou r 16- bit da ta re gisters an d two co ntrol re gister. th e co ntrol register is located in bank1 and the other registers are located in bank0. read and write operations to the flash memory are carried out in 16-bit data operations using the address and data registers and the control register . several registers control the overall operation of the internal flash program memory. t he address registers are named farl and farh, the data registers are named fdnl and fdnh, and the control registers are named fcr and frcr. as the farl and fdnl registers are located in bank 0, they can be directly accessed in the same was as any other special function register. the farh, fdnh, fcr and frcr registers however, being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1.
rev. 1.10 ?0 ??ne 10? ?01? rev. 1.10 ? 1 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi program memory register list ? HT68FB540 name bit 7 6 5 4 3 2 1 0 farl d7 d6 d5 d4 d ? d ? d1 d0 farh d11 d10 d9 d8 fd0l d7 d6 d5 d4 d ? d ? d1 d0 fd0h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fd1l d7 d6 d5 d4 d ? d ? d1 d0 fd1h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fd ? l d7 d6 d5 d4 d ? d ? d1 d0 fd ? h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fd ? l d7 d6 d5 d4 d ? d ? d1 d0 fd ? h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fcr cfwen fmod ? fmod1 fmod0 bwt fwt frden frd frcr fswrst clwb ? ht68fb550 name bit 7 6 5 4 3 2 1 0 farl d7 d6 d5 d4 d ? d ? d1 d0 farh d1 ? d11 d10 d9 d8 fd0l d7 d6 d5 d4 d ? d ? d1 d0 fd0h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fd1l d7 d6 d5 d4 d ? d ? d1 d0 fd1h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fd ? l d7 d6 d5 d4 d ? d ? d1 d0 fd ? h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fd ? l d7 d6 d5 d4 d ? d ? d1 d0 fd ? h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fcr cfwen fmod ? fmod1 fmod0 bwt fwt frden frd frcr fswrst clwb ? ht68fb560 name bit 7 6 5 4 3 2 1 0 farl d7 d6 d5 d4 d ? d ? d1 d0 farh d1 ? d1 ? d11 d10 d9 d8 fd0l d7 d6 d5 d4 d ? d ? d1 d0 fd0h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fd1l d7 d6 d5 d4 d ? d ? d1 d0 fd1h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fd ? l d7 d6 d5 d4 d ? d ? d1 d0 fd ? h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fd ? l d7 d6 d5 d4 d ? d ? d1 d0 fd ? h d15 d14 d1 ? d1 ? d11 d10 d9 d8 fcr cfwen fmod ? fmod1 fmod0 bwt fwt frden frd frcr fswrst - clwb
rev. 1.10 ?? ?? ne 10 ? ? 01 ? rev. 1.10 ?? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi farl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" ? nknown bit 7~0 d7~d0 : flash program memory address flash program memory address bit 7~bit 0 farh register HT68FB540 bit 7 6 5 4 3 2 1 0 name d11 d10 d9 d8 r/w r/w r/w r/w r/w por x x x x "x" ? nknown bit 7~4 reserved, cannot be used bit 3~0 d11~d8 : flash program memory address flash program memory address bit 11~bit 8 ? ht68fb550 bit 7 6 5 4 3 2 1 0 name d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w por x x x x x "x" ? nknown bit 7~5 reserved, cannot be used bit 4~0 d12~d8 : flash program memory address flash program memory address bit 12~bit 8 ? ht68fb560 bit 7 6 5 4 3 2 1 0 name d1 ? d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w por x x x x x x "x" ? nknown bit 7~6 reserved, cannot be used bit 5~0 d13~d8 : flash program memory address flash program memory address bit 13~bit 8
rev. 1.10 ?? ??ne 10? ?01? rev. 1.10 ?? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi fcr register bit 7 6 5 4 3 2 1 0 name cfwen fmod ? fmod1 fmod0 bwt fwt frden frd r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 cfwen : flash rom write enable bit, fwen, control bit 0: disable 1: unimplemented this bit is used to control the fwen bit enable or disable. when this bit is cleared to low by software, the flash memory write enable control bit, fwen will be cleared to low as well. its ineffective to set this bit to high. the user can check thi s bit to confrm the fwen status. bit 6~4 fmod2~fmod0 : flash program memory, confguration option memory operating mode control bits 000: write memory mode 001: page erase mode 010: reserved 011: read memory mode 100: reserved 101: reserved 110: fwen (fash memory write enable) bit control mode 111: reserved bit 3 bwt : mode change control 0: mode change cycle has fnished 1: activate a mode change cycle this bit will be automa tically reset to zero by the hardwa re afte r the mode change cycle has fnished. bit 2 fwt : flash memory write control 0: write cycle has fnished 1: activate a write cycle this is the flash memory write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. bit 1 frden : flash memory read enable 0: disable 1: enable this is the fla sh me mory re ad ena ble bi t whi ch must be set hi gh be fore fla sh memory read operati ons are carrie d out. clea ring thi s bit to zero will inhi bit flash memory read operations. bit 0 frd : flash memory read control 0: read cycle has fnished 1: activate a read cycle this is the flash memory read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the fwt , frden and frd registers can not be set to "1" at the same time with a single instruction.
rev. 1.10 34 june 10. 2013 rev. 1.10 35 june 11, 2013 HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi frcr register bit 7 6 5 4 3 2 1 0 name fswrst clwb r/w r/w r/w por 0 0 bit 7~5 "": unimplemented, read as "0" bit 4 fswrst: control bit must be to 0 bit 3~1 "": unimplemented, read as "0" bit 0 clwb : flash program memory write buffer clear control bit 0: do not initiate clear write buf fer or clear process 1: initiate clear write buf fer process this bit is used to control the flash program memory clear write buffer process. it will be set by software and cleared by hardware. in application program C iap offering users the convenience of flash memory multi-programming feature s , the ht68fb5x0 series of devices not only provide an isp function, but also an additional iap function. the convenience of the iap function is that it can execute the updated program procedure using its internal frmware, without requiring an external program writer or pc. in addition, the iap interface can also be any type of communication protocol, such as uart or can, using i/o pins. designers can assign i/o pins to communicate with the external memory device, including the updated program. regarding the internal firmware, the user can select version s provided by holtek or create their own. the following section illustrates the procedure s regarding how to implement iap frmware. enable flash write control procedure the first procedure to implement the iap firmware is to enable the flash write control which includes the following steps. ? write data "110" to the fmod [2:0] bits in the fcr register to enable the flash write control bit, fwen. ? set the bwt bit in the fcr register to "1". ? the device will start a 1ms counter. the user should write the correct data pattern into the flash data registers, namely fd1l~fd3l and fd1h~fd3h, during this period of time. ? once the 1ms counter has overfowed or if the written pattern is incorrect , the enable flash write control procedure will be invalid and the user should repeat the above procedure. ? no matter whether the procedure is valid or not , t he devices will clear the bwt bit automatically. ? the enable flash write pattern data is (00h 04h 0dh 09h c3h 40h) and it should be written into the flash data registers. ? once the flash write operation is enabled, the user can update the flash memory using the flash control registers. ? to disable the flash write procedure, the user can only clear the cfwen bit in the fcr register. there is no need to execute the above procedure.
rev. 1.10 ?4 ??ne 10? ?01? rev. 1.10 ? 5 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi set fwen fmod2~0 = 110 : set fwen bit bwt = 1,hardware set a counter wrtie the following pattern to flash data register fd 1l= 00h , fd 1h = 04h fd 2l = 0dh , fd 2h = 09h fd 3l =c 3h , fd 3h = 40h is pattern is correct ? cfwen=0 set fwen bit fail no cfwen=1 set fwen bit success . yes end is counter overflow? no yes bwt=0?
rev. 1.10 ? 6 ?? ne 10 ? ? 01 ? rev. 1.10 ?7 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi flash memory write and read procedures the following fow charts illustrate the write and read flash memory procedures. write flash rom set fwen procedure fwt=1 flash address register: fah=xxh, fal=xxh write the following data to register: fd0l=xxh, fd0h=xxh yes page erase fah=xxh, fal=xxh fmod2~0=001 fwt=1 fwt=0 ? yes no write fmod2~0=000 clear cfwen bit end write finish ? yes no write data to write buffer [(rom 8k 1~32 words dat a) or (rom > 8k 1~64 words dat a)]: write buffer finish? no write next page write next data yes fwt=0 ? no write flash program rom procedure
rev. 1.10 ?6 ??ne 10? ?01? rev. 1.10 ? 7 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi read flash read flash program or configuration option procedure frden=0 clear cfwen bit end read finish ? yes no fmod2~0=011 frden=1 flash address register: fah=xxh, fal=xxh frd=0 ? yes no read value: fd0l=xxh, fd0h=xxh frd=1 read flash program procedure
rev. 1.10 ? 8 ?? ne 10 ? ? 01 ? rev. 1.10 ?9 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi in circuit programming C icp the provision of fla sh ty pe pro gram mem ory pr ovides th e use r wit h a me ans of co nvenient an d easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or up grading th e pro gram at a la ter sta ge. th is e nables p roduct ma nufacturers t o ea sily keep their manufactured products supplied with the latest program releases without removal and re- insertion of the device. holtek writer pins mcu programming pins pin description icpda udn programming serial data icpck res programming clock vdd vdd/hvdd power s ? pply vss vss gro ? nd the program memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, taking control of the udn and res pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
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?? note: * may be resist or or capaci tor. the resista nce of * must be greater tha n 300 w or the capacitance of * must be less than 1nf. on-chip debug support C ocds there is an ev chip named ht68v b540/ht68vb550/ht68vb560 which is used to emulate the HT68FB540/ht68fb550/ht68fb560 device. the ht68vb540/ht68vb550/ht68vb560 device also provides the on-chip debug function to debug the HT68FB540/ht68fb550/ht68fb560 device during development process. the two devices, HT68FB540/ht68fb550/ht68fb560 and ht68vb540/ht68vb550/ht68vb560, are almost functional compatible except the on-chip debug function. users can use the ht68vb540/ht68vb550/ht68vb560 device to emulate the HT68FB540/ht68fb550/ht68fb560 device behaviors by connecting the ocdsda and ocdsck
rev. 1.10 ?8 ??ne 10? ?01? rev. 1.10 ? 9 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/ output pin while the ocdsck pin is the ocds clock input pin. when users use the ht68vb540/ ht68vb550/ht68vb560 ev ch ip fo r de bugging, th e co rresponding pi n fu nctions sha red wit h th e ocdsda and ocdsck pins in the HT68FB540/ht68fb550/ht68fb560 device will have no ef fect in the ht68vb540/ht68vb550/ht68vb560 ev chip. for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip deb ? g s ? pport data/address inp ? t/o ? tp ? t ocdsck ocdsck on-chip deb ? g s ? pport clock inp ? t vdd vdd/hvdd power s ? pply gnd vss gro ? nd ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. her e ar e lo cated re gisters whi ch ar e ne cessary fo r co rrect op eration of th e de vice. man y of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. device capacity banks HT68FB540 ? 56 8 0: 80h~ffh 1: 80h~ffh ht68fb550 51 ? 8 0: 80h~ffh 1: 80h~ffh ? : 80h~ffh ? : 80h~ffh ht68fb560 768 8 0: 80h~ffh 1: 80h~ffh ? : 80h~ffh ? : 80h~ffh 4: 80h~ffh 5: 80h~ffh the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into several banks, the structure of which depends upon the device chosen. the special purpose data memory registers are accessible in all banks, with the exception of the frcr, fcr, farh and fdnh registers at address from 40h to 46h, which are only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h.
rev. 1.10 40 ?? ne 10 ? ? 01 ? rev. 1.10 41 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

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rev. 1.10 40 ??ne 10? ?01? rev. 1.10 41 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

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rev. 1.10 4 ? ?? ne 10 ? ? 01 ? rev. 1.10 4? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

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rev. 1.10 4? ??ne 10? ?01? rev. 1.10 4 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi special function register description most of the speci al funct ion regi ster det ails will be descri bed in the rel evant functi onal sect ion; however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal regist ers. the me thod of i ndirect addre ssing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from ba nk 0 whi le t he iar1 and mp1 regist er pa ir c an access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory poi nters, kn own as mp0 an d mp1 ar e pr ovided. th ese mem ory poi nters ar e physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data fro m a ll ba nks a ccording to b p re gister. di rect addre ssing ca n onl y b e use d wi th ba nk 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mo v a,04h ; setup size of block mo v block,a mov a, offset adre s1 ; ac cumulator lo aded wi th fr st ra m add ress mov mp 0,a ; se tup me mory poi nter wit h fr st ra m ad dress loop: clr ia r0 ; cl ear th e da ta at add ress de fned by mp 0 in c mp0 ; increment memory pointer sd z block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc ram addresses.
rev. 1.10 44 ?? ne 10 ? ? 01 ? rev. 1.10 45 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bank pointer C bp depending upon which device is used, the program and data memory are divided into several banks. selecting the required program and data memory area is achieved using the bank pointer. bit 5 of the bank pointer is used to select program memory bank 0 or 1, while bits 0~2 are used to select data memory banks 0 ~ 5. the data memory is initialis ed to bank 0 after a res et, except for a wdt time-out reset in the p ower down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function regist ers can be acce ssed from withi n any bank. direct ly addressi ng the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. as both the program memory and data memory share the same bank pointer register, care must be taken during programming. device bit 7 6 5 4 3 2 1 0 HT68FB540 dmbp0 ht68fb550 dmbp1 dmbp0 ht68fb560 pmbp0 dmbp ? dmbp1 dmbp0 bp registers list bp register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r r r r r r r r/w por 0 0 0 0 0 0 0 0 bit 7~1 "": unimplemented, read as "0" bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 ? ht68fb550 bit 7 6 5 4 3 2 1 0 name dmbp1 dmbp0 r/w r r r r r r r/w r/w por 0 0 0 0 0 0 0 0 bit 7~2 "": unimplemented, read as "0" bit 1~0 dmbp1, dmbp0 : select data memory banks 00: bank 0 01: bank 1 10: bank 2 11: bank 3
rev. 1.10 44 ??ne 10? ?01? rev. 1.10 45 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb560 bit 7 6 5 4 3 2 1 0 name pmbp0 dmbp ? dmbp1 dmbp0 r/w r r r/w r r r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 "": unimplemented, read as "0" bit 5 pmbp0 : select program memory banks 0: bank 0, program memory address is from 0000h ~ 1fffh 1: bank 1, program memory address is from 2000h ~ 3fffh bit 4~3 "": unimplemented, read as "0" bit 2~0 dmbp2 ~ dmbp0 : select data memory banks 000: bank 0 001: bank 1 010: bank 2 011: bank 3 100: bank 4 101: bank 5 110~111: unimplemented accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logic al opera tion such as addit ion, subtrac tion, shift , etc ., to the dat a mem ory resulting in higher programm ing and tim ing overheads. data tra nsfer operations usually invol ve the temporary stora ge funct ion of the acc umulator; for ex ample, whe n tra nsferring dat a bet ween one user defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program mem ory. tbl p and tbhp are the ta ble point er and indi cates the loc ation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.10 46 ?? ne 10 ? ? 01 ? rev. 1.10 47 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the "clr wdt" or "halt" instruction. the pdf fag is affected only by executing the "halt" or "clr wdt" instruction or during a system power -up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "hal t" instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r r r/w r/w r/w r/w por 0 0 0 0 x x x x "x" ? nknown bit 7~6 "": unimplemented, read as "0" bit 5 to : watchdog time-out fag 0: after power up or executing the "clr wdt" or "hal t" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero
rev. 1.10 46 ??ne 10? ?01? rev. 1.10 47 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer interrupt. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of bot h fast and slow syste m osci llators. the hig h spee d osci llator, hxt or hirc, option is selected through the confguration option. the higher frequency oscillators provide higher performance bu t ca rry wit h it th e di sadvantage of hi gher po wer re quirements, whi le th e op posite is of course true for the lower frequency oscillator . with the capability of dynamically switching between fast and slow sys tem clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. type name freq. pins external crystal hxt 6mhz or 1 ? mhz osc1/osc ? internal high speed rc hirc 1 ? mhz internal low speed rc lirc ?? khz oscillator types note: for usb applications, hxt must be connected an 6mhz or 12mhz crystal. system clock confgurations there are several oscillator sources , two high speed oscillators and one low speed oscillator . the high speed system clocks are sourced from the external crystal/ ceramic oscillator, the pll frequency generator and the internal 12mhz rc oscillator. the low speed oscillator is the internal 32khz rc oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is impl emented using the hlclk bit and cks2~cks0 bits in the smod regist er and as the system clock can be dynamically selected. the actual source clock used for each of the high speed oscillators is chosen via confguration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2~cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. in addition, the internal pll frequency generator, whose clock source is supplied by an external crystal oscillator, can be enabled by a software control bit to generate various frequencies for the usb interface and system clock.
rev. 1.10 48 ?? ne 10 ? ? 01 ? rev. 1.10 49 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi hxt o sc ? config . option selects 6 or 1? mh z xtal high speed oscillator 6 mh z sysclk bit pll pll bit 48 mhz usbcken bit to usbck circ?its 16 mhz 1? mhz 6 mhz sysclk bit h osc config?ration option h osc pll clock pll bit f sys 16 mhz bit f h lirc o sc h irc o sc usbcken bit prescaler f h /? f h /4 f h /8 f h / 16 f h / ?? f h / 64 f sys f h f l wdt hclk bit cks 0- cks ? bit f l fast wake- up from sleep or idle mode control ( for hxt only ) h osc f sub system clock confgurations external crystal oscillator C hxt the external crystal system oscillator is one of the high frequency oscillator.
? ? ?? crystal/ceramic system oscillator C hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 16mhz 0pf 0pf 1 ? mhz 0pf 0pf 8mhz 0pf 0pf 6mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf note: 1. c1 and c ? val ? es are for g ? idance only. crystal recommended capacitor values note: for usb applications, hxt must be connected a 6mhz or 12mhz crystal.
rev. 1.10 48 ??ne 10? ?01? rev. 1.10 49 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi internal pll frequency generator the internal pll freque ncy generator is used to generate the frequency for the usb interface and the system clock. this pll generator can be enabled or disabled by the pll control bit in the usc register. after a power on reset, the pll control bit will be set to "0" to turn on the pll generator. the pll generator will provide the fxed 48mhz frequency for the usb operating frequency and another frequency for the system clock source which can be either 6mhz, 12mhz or 16mhz . the selection of this system frequency is implemented using the sysclk, fsys16mhz, and usbcken bits in the ucc register. in addition, the system clock can be selected as the hxt via these control bits. the clk_adj bit is used to adj ust the pll clock automatically . sysc register bit 7 6 5 4 3 2 1 0 name clk_ad ? usbdis rubus hfv r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 clk_adj : pll clock automatic adjustment function: 0: disable 1: enable note that if the user selects the hirc as the system clock, the clk_adj bit must be set to "1" to adjust the pll frequency automatically . bit 6 usbdis : usb sie control bit usb related control bit, described elsewhere bit 5 rubus : ubus pin pull low resistor usb related control bit, described elsewhere bit 4~3 "": unimpleme nted, read as "0" bit 2 hfv : non-usb mode high frequency voltage control 0: for usb mode - bit must be cleared to zero. 1: for non-usb mode - bit must be set high. ensures that the higher frequency can work at lower voltages. a higher frequency is >8mhz and is used for the system clock f h . bit 1~0 "": unimpleme nted, read as "0" ucc register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name rctrl sysclk fsys16mhz susp ? usbcken eps1 eps0 r/w r/w r/w r/w r/w r/w r r/w r/w por 0 0 0 0 0 0 0 0 b it 7 rctrl : 7.5k resistor between udp and ubus control bit usb related control bit, described elsewhere bit 6 sysclk : system clock frequency select bit 0: 12mhz 1: 6mhz note: if a 6 mhz crystal or resonator is used for the mcu, this bit should be set to "1". if a 12 mhz crystal or resonator is used, then this bit should be set to "0". if the 12mhz hirc is selected, then this bit must be set to "0". bit 5 fsys16mhz : pll 16mhz output control bit 0: hxt 1: pll 16mhz
rev. 1.10 50 ?? ne 10 ? ? 01 ? rev. 1.10 51 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 4 susp2 : reduce power consumption in suspend mode control bit usb related control bit, described elsewhere bit 3 usbcken : usb clock control bit 0: disable 1: enable bit 2 "": unimplemented, read as "0" bit 1~0 eps1, eps0 : accessing endpoint fifo selection usb related control bit, described elsewhere usc register bit 7 6 5 4 3 2 1 0 name urd selps ? pll selusb resume urst rmwk susp r/w r/w r/w r/w r/w r r/w r/w r por 1 0 0 0 0 0 0 0 b it 7 urd : usb reset signal control function defnition usb related control bit, described elsewhere bit 6 selps2 : the chip works under ps2 mode indicator bit usb related control bit, described elsewhere bit 5 pll : pll control bit 0: turn-on pll 1: turn-off pll bit 4 selusb : the chip works under usb mode indicator bit usb related control bit, described elsewhere bit 3 resume : usb resume indication bit usb related control bit, described elsewhere bit 2 urst : usb reset indication bit usb related control bit, described elsewhere bit 1 rmwk : usb remote wake-up command usb related control bit, described elsewhere bit 0 susp : usb suspend indication usb related control bit, described els ewhere the following table illustrates the pll output frequency selected by the related control bits. pll usbcken fsys16mhz f h 0 0 0 hosc (hxt or hirc) 0 0 1 f pll C 16mhz 0 1 0 f pll C 6mhz or 1 ? mhz ? depending on the "sysclk" bit in the ucc register selection 0 1 1 f pll C 16mhz 1 x x hosc (hxt or hirc) x: stand for "dont care" high frequency system clock f h selection table
rev. 1.10 50 ??ne 10? ?01? rev. 1.10 51 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency ar e mi nimised. as a re sult, at a po wer sup ply of ei ther 3. 3v or 5v an d at a temperature of 25 degrees, the fxed oscillation frequency of 12mhz will have a tolerance within 3% (non-usb mode). note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pi ns pa1 and pa2 are free for use as normal i/o pins. the h i rc has its own power supply pin, hvdd. the hvdd pin must be connected to vdd and an 0.1 m f capacitor to ground. internal 32khz oscillator C lirc the internal 32khz system oscillator is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary internal clocks the low speed osci llator, in addit ion to providing a system cloc k source is also used to provide a clock source, namely f sub , to the watchdog timer interrupt. operating modes and system clocks present day applicati ons require that their microcontrol lers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powere d porta ble appl ications. the fast cl ocks requi red for high perform ance wil l by their nature inc rease curr ent consu mption and of cour se vic e versa , lowe r spee d cl ocks redu ce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main syst em cl ock, ca n co me fr om ei ther a hi gh fr equency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either a hx t or hirc oscillator , selected via a configuration option. the low speed system clock source can be provided by internal clock f l , sourced by the lirc oscillator. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. t he f sub clock is used as the clock source for the watchdog timer .
rev. 1.10 5 ? ?? ne 10 ? ? 01 ? rev. 1.10 5? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi hxt o sc ? config . option selects 6 or 1? mh z xtal high speed oscillator 6 mh z sysclk bit pll pll bit 48 mhz usbcken bit to usbck circ?its 16 mhz 1? mhz 6 mhz sysclk bit h osc config?ration option h osc pll clock pll bit f sys 16 mhz bit f h lirc o sc h irc o sc usbcken bit prescaler f h /? f h /4 f h /8 f h / 16 f h / ?? f h / 64 f sys f h f l wdt hclk bit cks 0- cks ? bit f l fast wake- up from sleep or idle mode control ( for hxt only ) h osc f sub system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the applicat ion. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the rem aining four mode s, the sle ep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f sub normal mode on f h ~ f h/64 on slow mode on f l on idle0 mode off off on idle1 mode off on on sleep0 mode off off off sleep1 mode off off on
rev. 1.10 5? ??ne 10? ?01? rev. 1.10 5 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source is provided by the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is low . in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer , tms and sim. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the watchdog timer clock, f sub , will be on. idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watch dog timer , tms and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the watchd og timer clock, f sub , will be on. sleep0 mode the sleep0 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped, and the f l clock will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to "0". if the lvden is set to "1", it wont enter the sleep0 mode. sleep1 mode the sleep1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however, the f sub clock will continue to operate if the lvden is "1" or the watchdog timer function is enabled .
rev. 1.10 54 ?? ne 10 ? ? 01 ? rev. 1.10 55 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi control register a single register , smod is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0 : the system clock selection when hlclk is "0". 000: f l ( f lirc ) 001: f l (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten : fast wake-up control (only for hxt ) 0: disable 1: enable this is the fast wake-up control bit which determines if the f l clock source is initially used after the de vice wakes up. whe n t he bi t i s hi gh, t he f l clock source c an be use d a s a temporary system clock to provide a faster wake up time as the f l clock is available. bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1~2 clock cycles if the lirc oscillator is used. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as "1" by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 1024 clock cycles if the hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will en ter th e idl e mode . in th e idl e1 mod e th e cpu wil l sto p run ning but the system cl ock wil l cont inue to kee p the peri pheral func tions oper ational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed.
rev. 1.10 54 ??ne 10? ?01? rev. 1.10 55 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the devi ce is up and running as fast as possibl e a fast wa ke-up funct ion is provided, which allows f l , namely the lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f l , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast wake-up function has no effect because the f l clock is stopped. the fast wake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscilla tor is select ed as the normal mode system cloc k, and if the fast wake-up function is enabled, then it will take one to two t l clock cycles of the lirc oscillator for the system to wake-up. the system will then initially run under the f l clock source until 1024 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator . if the hirc oscillator or lirc oscillator is used as the system oscillator then it will take 1024 clock cycles of the hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no ef fect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 10 ? 4 hxt cycles 10 ? 4 hxt cycles 1~ ? hxt cycles 1 10 ? 4 hxt cycles 1~ ? f l cycles (system r ? ns with f l frst for 10 ? 4 hxt cycles and then switches over to r ? n with the hxt clock) 1~ ? hxt cycles hirc x 10 ? 4 hirc cycles 10 ? 4 hirc cycles 1~ ? hirc cycles lirc x 1~ ? lirc cycles 1~ ? lirc cycles 1~ ? lirc cycles wake-up times note that if the watchdog timer is disabled, which means that the lirc is off, then there will be no fast wake-up function available when the device wakes-up from the sleep0 mode.
rev. 1.10 56 ?? ne 10 ? ? 01 ? rev. 1.10 57 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

? ? ?? ?

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? operating mode switching and wake-up the device can swit ch betwe en operati ng modes dynami cally all owing the user to sel ect the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h, to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when the device moves between the various operating modes. normal mode to slow mode switching when running in th e normal mod e, whi ch use s th e hi gh spe ed syst em osc illator, an d th erefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the l to bit in the smod register .
rev. 1.10 56 ??ne 10? ?01? rev. 1.10 57 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi
? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?- ?? ? ? -?? ? ? ? ? ? ? ?- ?? ?? -? ?
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rev. 1.10 58 ?? ne 10 ? ? 01 ? rev. 1.10 59 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi slow mode to normal mode switching in slow mode the system uses the lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "011", "100", "101", "110"or "11 1". as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the "h alt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and wdt clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0"and the wdt or lvd on. whe n thi s inst ruction is exe cuted under the condi tions desc ribed above , the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction , but the wdt or l vd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared.
rev. 1.10 58 ??ne 10? ?01? rev. 1.10 59 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "h alt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ct rl re gister eq ual to "0". wh en th is in struction is ex ecuted und er th e co nditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" in struction, but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the "h alt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in ct rl re gister eq ual to "1". wh en th is in struction is ex ecuted und er th e co nditions described above, the following will occur: ? the system clock and f sub clock will be on and the application program will stop at the"h alt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, the re are othe r consi derations whic h must al so be ta ken int o ac count by the ci rcuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonded pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the lirc oscillator is enabled. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps
rev. 1.10 60 ?? ne 10 ? ? 01 ? rev. 1.10 61 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external or usb reset ? an external rising or falling edge on pa and a falling edge on pb~pe, except for pe1 ? a system interrupt ? a wdt overfow if the system is woken up by an external or usb reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the "halt" instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on ports can be setup using the pa wu and pxwu registers to permit a negative transition on the pin to wake-up the system. when a port pin wake-up occurs, the program will resume execution at th e in struction fo llowing th e "halt " in struction. if th e syste m is woke n up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations ? if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after ht o is " 1". ? if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hx t os cillator an d fs ten is "1", the system clock can be switched to the lirc oscillator after wake up. ? there are peripheral functions, such as wdt, tms and sim, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/off condition of f l depends upon whether the wdt is enabled o r disabled as the wdt clock source is generated from f l .
rev. 1.10 60 ??ne 10? ?01? rev. 1.10 61 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f sub, which is sourced from the lirc oscillator. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with vdd, temperature and process variations. the wdt function is allowed to enable or disable by setting the wdtc register data. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. the wrf software reset fag will be indicated in the ctrl register . wdtc register bit 7 6 5 4 3 2 1 0 name we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4~we0 : wdt function software control 10101: wdt disabled 01010: wdt enabled other values: reset mcu when these bi ts ar e ch anged to an y ot her va lues du e to en vironmental no ise th e microcontroller will be reset; this reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1 to indicate the reset source. bit 2~0 ws2, ws1, ws0 : wdt time-out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period.
rev. 1.10 6 ? ?? ne 10 ? ? 01 ? rev. 1.10 6? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson : f sys control in idle mode described elsewhere. bit 6~3 "": unimplemented, read as "0" bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 lrf : lvr control register software reset fag described elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application progra m. note tha t thi s bit ca n onl y be cl eared to 0 by the app lication program. watchdog timer operation the watchdog ti mer opera tes by providi ng a devi ce reset when it s ti mer overfows. thi s me ans that in the application progra m and duri ng norm al opera tion the user has to stra tegically cl ear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. with regard to the watchdog timer enable/disable function, there are also fve bits, we4~we0, in the wdtc register to offer additional enable/disable and reset control of the watchdog timer . wdt enable/disabled using the wdt control register the wdt is enabled/disabled using the wdt control register, the we4~we0 values can determine which mode the wdt operates in. the wdt will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bit value is equal to 01010b. if the we4~we0 bit s are set to an y othe r val ues othe r th an 0101 0b an d 1010 1b, it wil l rese t th e device after 2~3 lirc clock cycles. after power on these bits will have the value of 01010b. wdt we4~we0 bits wdt function controlled by wdt control register 10101b disable 01010b enable any other val ? e reset mcu watchdog timer enable/disable control under normal program opera tion, a wa tchdog ti mer ti me-out wil l ini tialise a devi ce rese t and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the watchdog timer contents. the frst is a wdt reset, which means a value other than 01010b or 10101b is written into the we4~we0 bit locations, the second is to use the watchdog timer software clear instructions and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer and that is to use the single "clr wdt" instruction to clear the wdt.
rev. 1.10 6? ??ne 10? ?01? rev. 1.10 6 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.

? ?? ?? ? ?- - ??? ?
?? ?? ? ? ? ?? ? ? ? ? watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. a hardware reset will of course be automatically implemented after the device is powered-on, however there are a number of other hardware and software reset sources that can be implemented dynamically when the device is running. reset overview the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defned state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program instructions commence execution. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. the devices provide several reset sources to generate the internal reset signal, providing extended mcu protection. the different types of resets are listed in the accompanying table. reset name abbreviation indication bit register notes power-on reset por a ? to generated at power on reset pin res hardware reset low voltage reset lvr lvrf ctrl low vdd voltage watchdog reset wdt to status wdtc register setting software reset wrf ctrl write to w dtc register lvrc register setting sofrware reset lrf ctrl write to lvrc register reset source summary in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontrolle r is alre ady running, the res line is forcefully pulled low. in such a case, kn own as a no rmal op eration re set, som e of the re gisters re main un changed al lowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all
rev. 1.10 64 ?? ne 10 ? ? 01 ? rev. 1.10 65 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most funda mental and unavoi dable rese t is the one tha t occ urs aft er power is frst appl ied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power -on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time= 50ms power-on reset timing chart res pin although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilis e quickly at power -on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. note: "*" it is recommended that this component is added for added esd protection
rev. 1.10 64 ??ne 10? ?01? rev. 1.10 65 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi "**" it is recommended that this component is added in environments where power line noise is signifcant. external res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. note: t rstd is power-on delay, typical time= 16.7ms res reset timing chart low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provide an mcu reset should the value fall below a certain predefned level. ? lvr operation the lvr function is always enabled with a specific lvr voltage v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery in battery powered applications, the lvr will automatically reset the device internally and the lvrf bit in the ctrl register will also be set to 1. for a valid lvr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the a.c. characteristics. if the low supply voltage state does not exceed this value, the lvr will ignore the low supply volt age and wil l not perform a rese t funct ion. the ac tual v lvr value can be selected by the lvs bits in the lvrc register. if the lvs7~l vs0 bits are changed to some different values by environmental noise, the lvr will reset the device after 2~3 lirc clock cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the power down mode. note: t rstd is power-on delay, typical time= 16.7ms low voltage reset timing chart
rev. 1.10 66 ?? ne 10 ? ? 01 ? rev. 1.10 67 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr voltage select control 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other value: generates mcu resetCregister is reset to por value when an actual low voltage condition occurs, as specified by one of the four defined lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles. in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned lvr values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation the register contents will be reset to the por value. ? ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson : f sys control in idle mode describe elsewhere. bit 6~3 "": unimplemented, read as "0" bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low voltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the lvrc register contains any non defned lvr voltage register values. this in effect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag describe elsewhere.
rev. 1.10 66 ??ne 10? ?01? rev. 1.10 67 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi watchdog time-out reset during normal operation the watchdog ti me-out reset during normal operat ion is the same as a hardwa re res pin rese t except that the watchdog time-out fag to will be set to "1". note: t rstd is power-on delay, typical time= 16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the con ditions rem ain uncha nged exc ept tha t the progra m counte r and the sta ck pointer will be cleared to "0" and the to fag will be set to "1". refer to the a.c. characteristics for t sst details. note:the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the t sst is 1024 clock for hxt. the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart ? wdtc register software reset a wdtc software reset will be generated when a value other than "10101" or "01010", exist in the highest fve bits of the wdtc register. the wrf bit in the ctrl register will be set high when this occurs, thus indicating the generation of a wdtc software reset. ? wdtc register bit 7 6 5 4 3 2 1 0 name we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4, we3, we2, we1, we0 : wdt software control 10101: wdt disable 01010: wdt enable (default) other: mcu reset bit 2~0 ws2, ws1, ws0 : wdt time-out period selection. described elsewhere
rev. 1.10 68 ?? ne 10 ? ? 01 ? rev. 1.10 69 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, suc h as th e sle ep or idl e mod e fu nction or wa tchdog ti mer. th e re set fl ags ar e shown in the table: to pdf reset conditions 0 0 power-on reset ? ? res ? lvr or usb reset d ? ring normal or slow mode operation 1 ? wdt time-o ? t reset d ? ring normal or slow mode operation 1 1 wdt time-o ? t reset d ? ring idle or sleep mode operation " ? "stands for ? nchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program co ? nter reset to zero interr ? pts all interr ? pts will be disabled wdt clear after reset ? wdt begins co ? nting timer/event co ? nter timer co ? nter will be t ? rned off inp ? t/o ? tp ? t ports i/o ports will be set ? p as inp ? ts stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type.
rev. 1.10 68 ??ne 10? ?01? rev. 1.10 69 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? the HT68FB540 register states are summarized below: register reset (power on) wdt time- out/wdtc software reset (normal operation) res reset/lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) mp0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx mp1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx acc xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? tbhp ---- xxxx ---- ???? ---- ???? ---- ???? ---- ???? ---- ???? ---- ???? status --00 xxxx --1 ? ?? ?? -- ?? ?? ?? --01 ???? --11 ???? -- ?? ?? ?? -- ?? ?? ?? bp ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- --- ? ---- ---0 ---- ---0 smod 0000 0011 0000 0011 0000 0011 0000 0011 ???? ???? 0000 0011 0000 0011 integ 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 lvdc --00 -000 --00 -000 --00 -000 --00 -000 -- ?? - ??? --00 -000 --00 -000 intc0 -000 0000 -000 0000 -000 0000 -000 0000 - ??? ???? -000 0000 -000 0000 intc1 00-0 00-0 00-0 00-0 00-0 00-0 00-0 00-0 ?? - ? ?? - ? 00-0 00-0 00-0 00-0 intc ? 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mfi0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mfi1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pa 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pb -111 1111 -111 1111 -111 1111 -111 1111 - ??? ???? -111 1111 -111 1111 pbc -111 1111 -111 1111 -111 1111 -111 1111 - ??? ???? -111 1111 -111 1111 pe ---- -101 ---- -101 ---- -101 ---- -101 ---- - ??? ---- -101 ---- -101 pec ---- -111 ---- -111 ---- -111 ---- -111 ---- - ??? ---- -111 ---- -111 wdtc 0101 0011 0101 0011 0101 0011 0101 0011 ???? ???? 0101 0011 0101 0011 frcr ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 -- - ? --- ? ---0 ---0 ---0 ---0 fcr 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 farl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx farh ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- ???? ---- xxxx ---- xxxx fd0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx i ? ctoc 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 simc0 1110 000- 1110 000- 1110 000- 1110 000- ???? ??? - 1110 000- 1110 000- simc1 1000 0001 1000 0001 1000 0001 1000 0001 ???? ???? 1000 0001 1000 0001
rev. 1.10 70 ?? ne 10 ? ? 01 ? rev. 1.10 71 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi register reset (power on) wdt time- out/wdtc software reset (normal operation) res reset/lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx sima/ simc ? 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 spiac0 111- --0- 111- --0- 111- --0- 111- --0- ??? - -- ? - 111- --0- 111- --0- spiac1 --00 0000 --00 0000 --00 0000 --00 0000 -- ?? ?? ?? --00 0000 --00 0000 spiad xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx sbsc 0000 ---0 0000 ---0 0000 ---0 0000 ---0 ???? --- ? 0000 ---0 0000 ---0 pawu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 padir 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 papu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pxpu -0-- --00 -0-- --00 -0-- --00 -0-- --00 - ? -- -- ?? -0-- --00 -0-- --00 pxwu -0-- --00 -0-- --00 -0-- --00 -0-- --00 - ? -- -- ?? -0-- --00 -0-- --00 tmpc0 --01 --01 --01 --01 --01 --01 --01 --01 -- ?? -- ?? --01 --01 --01 --01 tmpc1 --01 --01 --01 --01 --01 --01 --01 --01 -- ?? -- ?? --01 --01 --01 --01 tm0c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- ???? ? --- 0000 0--- 0000 0--- tm0c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0dh 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0ah 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0rp 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1c0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1dh ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm1al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1ah ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? c0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dh ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? ah ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? c0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dh ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? ah ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 usb_ stat 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000-
rev. 1.10 70 ??ne 10? ?01? rev. 1.10 71 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi register reset (power on) wdt time- out/wdtc software reset (normal operation) res reset/lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) uint ---- 0000 ---- ???? ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 usc 1000 0000 ???? x ?? x 1000 0000 1000 0000 ???? x ?? x 1 ??? 0100 1 ??? 0100 usr ---- 0000 ---- ???? ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 ucc 0000 0-00 ???? ? - ?? 0000 0-00 0000 0-00 ???? ? - ?? 0 ?? 0 ? - 00 0 ?? 0 ? - 00 awr 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 stli ---- 0000 ---- ???? ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 stlo ---- 0000 ---- ???? ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 sies 00-0 0000 ?? -x x ??? 00-0 0000 00-0 0000 ?? -x x ??? 00-0 0000 00-0 0000 misc 000- 0000 xx ? - ???? 000- 0000 000- 0000 xx ? - ???? 000- 0000 000- 0000 ufien ---- 0000 ---- ???? ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 fifo0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo ? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo ? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ufoen ---- 0000 ---- ???? ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 ufc0 0000 00-- ???? ?? -- 0000 00-- 0000 00-- ???? ?? -- 0000 00-- 0000 00-- paps0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 paps1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 sysc 000 - -0- - 000 - -0- - 000 - -0- - 000 - -0- - ??? - - ? - - 000 - -0- - 000 - -0- - ctrl 0--- -x00 0--- -x00 0--- -x00 0--- -x00 ? --- -x ?? 0--- -x00 0--- -x00 lvrc 0101 0101 0101 0101 0101 0101 0101 0101 ???? ???? 0101 0101 0101 0101 note: " * " stands for "warm reset" " - " not implement " u " stands for "unchanged" " x " stands for "unknown"
rev. 1.10 7 ? ?? ne 10 ? ? 01 ? rev. 1.10 7? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? the ht68fb550 register states are summarized below: register reset (power on) wdt time- out/wdtc software reset (normal operation) res reset/lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) mp0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx mp1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx acc xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? tbhp ---x xxxx --- ? ???? --- ? ???? --- ? ???? --- ? ???? --- ? ???? --- ? ???? status --00 xxxx --1 ? ?? ?? -- ?? ?? ?? --01 ???? --11 ???? -- ?? ?? ?? -- ?? ?? ?? bp ---- --00 ---- ---00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 smod 0000 0011 0000 0011 0000 0011 0000 0011 ???? ???? 0000 0011 0000 0011 integ 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 lvdc --00 -000 --00 -000 --00 -000 --00 -000 -- ?? - ??? --00 -000 --00 -000 intc0 -000 0000 -000 0000 -000 0000 -000 0000 - ??? ???? -000 0000 -000 0000 intc1 00-0 00-0 00-0 00-0 00-0 00-0 00-0 00-0 ?? - ? ?? - ? 00-0 00-0 00-0 00-0 intc ? 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mfi0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mfi1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pa 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pb -111 1111 -111 1111 -111 1111 -111 1111 - ??? ???? -111 1111 -111 1111 pbc -111 1111 -111 1111 -111 1111 -111 1111 - ??? ???? -111 1111 -111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pe ---- -101 ---- -101 ---- -101 ---- -101 ---- - ??? ---- -101 ---- -101 pec ---- -111 ---- -111 ---- -111 ---- -111 ---- - ??? ---- -111 ---- -111 wdtc 0101 0011 0101 0011 0101 0011 0101 0011 ???? ???? 0101 0011 0101 0011 frcr ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 -- - ? --- ? ---0 ---0 ---0 ---0 fcr 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 farl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx farh ---x xxxx ---x xxxx ---x xxxx ---x xxxx --- ? ???? ---x xxxx ---x xxxx fd0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx
rev. 1.10 7? ??ne 10? ?01? rev. 1.10 7 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi register reset (power on) wdt time- out/wdtc software reset (normal operation) res reset/lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) i ? ctoc 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 simc0 1110 000- 1110 000- 1110 000- 1110 000- ???? ??? - 1110 000- 1110 000- simc1 1000 0001 1000 0001 1000 0001 1000 0001 ???? ???? 1000 0001 1000 0001 simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx sima/ simc ? 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 spiac0 111- --0- 111- --0- 111- --0- 111- --0- ??? - -- ? - 111- --0- 111- --0- spiac1 --00 0000 --00 0000 --00 0000 --00 0000 -- ?? ?? ?? --00 0000 --00 0000 spiad xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx sbsc 0000 ---0 0000 ---0 0000 ---0 0000 ---0 ???? --- ? 0000 ---0 0000 ---0 pawu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 padir 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 papu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pxpu -000 --00 -000 --00 -000 --00 -000 --00 - ??? -- ?? -000 --00 -000 --00 pxwu -000 --00 -000 --00 -000 --00 -000 --00 - ??? -- ?? -000 --00 -000 --00 tmpc0 --01 --01 --01 --01 --01 --01 --01 --01 -- ?? -- ?? --01 --01 --01 --01 tmpc1 --01 --01 --01 --01 --01 --01 --01 --01 -- ?? -- ?? --01 --01 --01 --01 tm0c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- ???? ? --- 0000 0--- 0000 0--- tm0c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0dh 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0ah 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0rp 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1c0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1dh ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm1al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1ah ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? c0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dh ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? ah ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? c0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dh ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00
rev. 1.10 74 ?? ne 10 ? ? 01 ? rev. 1.10 75 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi register reset (power on) wdt time- out/wdtc software reset (normal operation) res reset/lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tm ? al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? ah ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 usb_ stat 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- uint --00 0000 -- ?? ?? ?? --00 0000 --00 0000 -- ?? ?? ?? --00 0000 --00 0000 usc 1000 0000 ???? x ?? x 1000 0000 1000 0000 ???? x ?? x 1 ??? 0100 1 ??? 0100 usr --00 0000 -- ?? ?? ?? --00 0000 --00 0000 -- ?? ?? ?? --00 0000 --00 0000 ucc 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0 ?? 0 ? 000 0 ?? 0 ? 000 awr 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 stli --00 0000 -- ?? ?? ?? --00 0000 --00 0000 -- ?? ?? ?? --00 0000 --00 0000 stlo --00 0000 -- ?? ?? ?? --00 0000 --00 0000 -- ?? ?? ?? --00 0000 --00 0000 sies 00-0 0000 ?? -x x ??? 00-0 0000 00-0 0000 ?? -x x ??? 00-0 0000 00-0 0000 misc 0000 0000 xx ?? ???? 0000 0000 0000 0000 xx ?? ???? 0000 0000 0000 0000 ufien --00 0000 -- ?? ?? ?? --00 0000 --00 0000 -- ?? ?? ?? --00 0000 --00 0000 fifo0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo ? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo ? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo4 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo5 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ufoen --00 0000 -- ?? ?? ?? --00 0000 --00 0000 -- ?? ?? ?? --00 0000 --00 0000 ufc0 0000 00-- ???? ?? -- 0000 00-- 0000 00-- ???? ?? -- 0000 00-- 0000 00-- ufc1 ---- 0000 ---- ???? ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 pdps 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 paps0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 paps1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 sysc 000 - -0- - 000 - -0- - 000 - -0- - 000 - -0- - ??? - - ? - - 000 - -0- - 000 - -0- - ctrl 0--- -x00 0--- -x00 0--- -x00 0--- -x00 ? --- -x ?? 0--- -x00 0--- -x00 lvrc 0101 0101 0101 0101 0101 0101 0101 0101 ???? ???? 0101 0101 0101 0101 note: " * " stands for "warm reset" " - " not implement " u " stands for "unchanged" " x " stands for "unknown"
rev. 1.10 74 ??ne 10? ?01? rev. 1.10 75 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? the ht68fb560 register states are summarized below: register reset (power on) wdt time- out/wdtc software reset (normal operation) res reset/lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) mp0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx mp1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx acc xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? tbhp --xx xxxx -- ?? ?? ?? -- ?? ?? ?? -- ?? ?? ?? -- ?? ?? ?? -- ?? ?? ?? -- ?? ?? ?? status --00 xxxx --1 ? ?? ?? -- ?? ?? ?? --01 ???? --11 ???? -- ?? ?? ?? -- ?? ?? ?? bp --0- -000 --0- --000 --0- -000 --0- -000 -- ? - - ??? --0- -000 --0- -000 smod 0000 0011 0000 0011 0000 0011 0000 0011 ???? ???? 0000 0011 0000 0011 integ 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 lvdc --00 -000 --00 -000 --00 -000 --00 -000 -- ?? - ??? --00 -000 --00 -000 intc0 -000 0000 -000 0000 -000 0000 -000 0000 - ??? ???? -000 0000 -000 0000 intc1 00-0 00-0 00-0 00-0 00-0 00-0 00-0 00-0 ?? - ? ?? - ? 00-0 00-0 00-0 00-0 intc ? 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mfi0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mfi1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pa 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pe --11 1101 --11 1101 --11 1101 --11 1101 -- ?? ?? ?? --11 1101 --11 1101 pec --11 1111 --11 1111 --11 1111 --11 1111 -- ?? ?? ?? --11 1111 --11 1111 wdtc 0101 0011 0101 0011 0101 0011 0101 0011 ???? ???? 0101 0011 0101 0011 frcr ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 -- - ? --- ? ---0 ---0 ---0 ---0 fcr 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 farl xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx farh --xx xxxx --xx xxxx --xx xxxx --xx xxxx -- ?? ?? ?? --xx xxxx --xx xxxx fd0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx
rev. 1.10 76 ?? ne 10 ? ? 01 ? rev. 1.10 77 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi register reset (power on) wdt time- out/wdtc software reset (normal operation) res reset/lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) fd ? l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx fd ? h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx i ? ctoc 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 simc0 1110 000- 1110 000- 1110 000- 1110 000- ???? ??? - 1110 000- 1110 000- simc1 1000 0001 1000 0001 1000 0001 1000 0001 ???? ???? 1000 0001 1000 0001 simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx sima/ simc ? 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 spiac0 111- --0- 111- --0- 111- --0- 111- --0- ??? - -- ? - 111- --0- 111- --0- spiac1 --00 0000 --00 0000 --00 0000 --00 0000 -- ?? ?? ?? --00 0000 --00 0000 spiad xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx sbsc 0000 ---0 0000 ---0 0000 ---0 0000 ---0 ???? --- ? 0000 ---0 0000 ---0 pawu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 padir 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 papu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pxpu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pxwu 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tmpc0 --01 --01 --01 --01 --01 --01 --01 --01 -- ?? -- ?? --01 --01 --01 --01 tmpc1 --01 --01 --01 --01 --01 --01 --01 --01 -- ?? -- ?? --01 --01 --01 --01 tm0c0 0000 0--- 0000 0--- 0000 0--- 0000 0--- ???? ? --- 0000 0--- 0000 0--- tm0c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0dh 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0ah 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm0rp 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1c0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1dh ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm1al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm1ah ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? c0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dh ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? ah ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? c0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000
rev. 1.10 76 ??ne 10? ?01? rev. 1.10 77 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi register reset (power on) wdt time- out/wdtc software reset (normal operation) res reset/lvrc software reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tm ? c1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dl 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? dh ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 tm ? al 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 tm ? ah ---- --00 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 usb_ stat 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- uint 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 usc 1000 0000 ???? x ?? x 1000 0000 1000 0000 ???? x ?? x 1 ??? 0100 1 ??? 0100 usr 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ucc 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0 ?? 0 ? 000 0 ?? 0 ? 000 awr 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 stli 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 stlo 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 sies 00-0 0000 ?? -x x ??? 00-0 0000 00-0 0000 ?? -x x ??? 00-0 0000 00-0 0000 misc 0000 0000 xx ?? ???? 0000 0000 0000 0000 xx ?? ???? 0000 0000 0000 0000 ufien 0000 0000 00 ?? ???? 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 fifo0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo ? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo ? xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo4 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo5 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo6 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx fifo7 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ufoen 0000 0000 00 ?? ???? -0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ufc0 0000 00-- ???? ?? -- 0000 00-- 0000 00-- ???? ?? -- 0000 00-- 0000 00-- ufc1 0000 0000 ???? ???? 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pdps 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 paps0 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 paps1 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 sysc 000 - -0- - 000 - -0- - 000 - -0- - 000 - -0- - ??? - - ? - - 000 - -0- - 000 - -0- - ctrl 0--- -x00 0--- -x00 0--- -x00 0--- -x00 ? --- -x ?? 0--- -x00 0--- -x00 lvrc 0101 0101 0101 0101 0101 0101 0101 0101 ???? ???? 0101 0101 0101 0101 note: " * " stands for "warm reset" " - " not implement " u " stands for "unchanged" " x " stands for "unknown"
rev. 1.10 78 ?? ne 10 ? ? 01 ? rev. 1.10 79 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi input/output ports holtek microcontrollers offe r consi derable fexi bility on the ir i/o ports. wi th the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the devices provide bidirectional input/output lines labeled with port names pa~pe. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list ? HT68FB540 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 padir d7 d6 d5 d4 d ? d ? d1 d0 pxwu pelwu pbhwu pblwu pxpu pelpu pbhpu pblpu paps0 pa ? s1 pa ? s0 pa ? s1 pa ? s0 pa1s1 pa1s0 pa0s1 pa0s0 paps1 pa7s1 pa7s0 pa6s1 pa6s0 pa5s1 pa5s0 pa4s1 pa4s0 pb d6 d5 d4 d ? d ? d1 d0 pbc d6 d5 d4 d ? d ? d1 d0 pe d ? d1 d0 pec d ? d1 d0
rev. 1.10 78 ??ne 10? ?01? rev. 1.10 79 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb550 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 padir d7 d6 d5 d4 d ? d ? d1 d0 pxwu pelwu pdhwu pdlwu pbhwu pblwu pxpu pelpu pdhpu pdlpu pbhpu pblpu paps0 pa ? s1 pa ? s0 pa ? s1 pa ? s0 pa1s1 pa1s0 pa0s1 pa0s0 paps1 pa7s1 pa7s0 pa6s1 pa6s0 pa5s1 pa5s0 pa4s1 pa4s0 pb d6 d5 d4 d ? d ? d1 d0 pbc d6 d5 d4 d ? d ? d1 d0 pd d7 d6 d5 d4 d ? d ? d1 d0 pdc d7 d6 d5 d4 d ? d ? d1 d0 pe d ? d1 d0 pec d ? d1 d0 ? ht68fb560 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d ? d ? d1 d0 papu d7 d6 d5 d4 d ? d ? d1 d0 pa d7 d6 d5 d4 d ? d ? d1 d0 pac d7 d6 d5 d4 d ? d ? d1 d0 padir d7 d6 d5 d4 d ? d ? d1 d0 pxwu pehwu pelwu pdhwu pdlwu pchwu pclwu pbhwu pblwu pxpu pehpu pelpu pdhpu pdlpu pchpu pclpu pbhpu pblpu paps0 pa ? s1 pa ? s0 pa ? s1 pa ? s0 pa1s1 pa1s0 pa0s1 pa0s0 paps1 pa7s1 pa7s0 pa6s1 pa6s0 pa5s1 pa5s0 pa4s1 pa4s0 pb d7 d6 d5 d4 d ? d ? d1 d0 pbc d7 d6 d5 d4 d ? d ? d1 d0 pc d7 d6 d5 d4 d ? d ? d1 d0 pcc d7 d6 d5 d4 d ? d ? d1 d0 pd d7 d6 d5 d4 d ? d ? d1 d0 pdc d7 d6 d5 d4 d ? d ? d1 d0 pe d5 d4 d ? d ? d1 d0 pec d5 d4 d ? d ? d1 d0
rev. 1.10 80 ?? ne 10 ? ? 01 ? rev. 1.10 81 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers, namely papu and pxpu, and are implemented using weak pmos transistors. note that the pa pull-high resistors are controlled by bits in the papu register, other than the pb, pc, pd, pe pull-high resistors are controlled by nibble in the pxpu register. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 papu : i/o pa bit 7~bit 0 pull-high control 0: disable 1: enable pxpu register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name pelpu pbhpu pblpu r/w r r/w r r r r r/w r/w por 0 0 0 0 0 0 0 0 bit 7 "": unimplemented, read as "0" bit 6 pelpu : pe2, pe0 pins pull-high control 0: disable 1: enable note that the pe1 pin has no pull-up resistor. bit 5~2 "": unimplemented, read as "0" bit 1 pbhpu : pb6~pb4 pins pull-high control 0: disable 1: enable bit 0 pblpu : pb3~pb0 pins pull-high control 0: disable 1: enable ? ht68fb550 bit 7 6 5 4 3 2 1 0 name pelpu pdhpu pdlpu pbhpu pblpu r/w r r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 0 0 bit 7 "": unimplemented, read as "0" bit 6 pelpu : pe2, pe0 pins pull-high control 0: disable 1: enable note that the pe1 pin has no pull-up resistor.
rev. 1.10 80 ??ne 10? ?01? rev. 1.10 81 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 5 pdhpu : pd7~pd4 pins pull-high control 0: disable 1: enable bit 4 pdlpu : pd3~pd0 pins pull-high control 0: disable 1: enable bit 3~2 "": unimplemented, read as "0" bit 1 pbhpu : pb6~pb4 pins pull-high control 0: disable 1: enable bit 0 pblpu : pb3~pb0 pins pull-high control 0: disable 1: enable ? ht68fb560 bit 7 6 5 4 3 2 1 0 name pehpu pelpu pdhpu pdlpu pchpu pclpu pbhpu pblpu r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pehpu : pe5~pe4 pins pull-high control 0: disable 1: enable bit 6 pelpu : pe3~pe2, pe0 pins pull-high control 0: disable 1: enable note that the pe1 pin has no pull-up resistor. bit 5 pdhpu : pd7~pd4 pins pull-high control 0: disable 1: enable bit 4 pdlpu : pd3~pd0 pins pull-high control 0: disable 1: enable bit 3 pchpu : pc7~pc4 pins pull-high control 0: disable 1: enable bit 2 pclpu : pc3~pc0 pins pull-high control 0: disable 1: enable bit 1 pbhpu : pb7~pb4 pins pull-high control 0: disable 1: enable bit 0 pblpu : pb3~pb0 pins pull-high control 0: disable 1: enable
rev. 1.10 8 ? ?? ne 10 ? ? 01 ? rev. 1.10 8? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi port wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a~port e pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a~port e can be selected by bits or nibble to have this wake-up feature using the pawu and pxwu registers. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 paw u : port a bit 7~bit 0 wake-up control 0: disable 1: enable pxwu register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name pelwu pbhwu pblwu r/w r r/w r r r r r/w r/w por 0 0 0 0 0 0 0 0 bit 7 "": unimplemented, read as "0" bit 6 pelwu : pe2, pe0 pins wake-up control 0: disable 1: enable note that the pe1 pin has no wake-up function. bit 5~2 "": unimplemented, read as "0" bit 1 pbhwu : pb6~pb4 pins wake-up control 0: disable 1: enable bit 0 pblwu : pb3~pb0 pins wake-up control 0: disable 1: enable ? ht68fb550 bit 7 6 5 4 3 2 1 0 name pelwu pdhwu pdlwu pbhwu pblwu r/w r r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 0 0 bit 7 "": unimplemented, read as "0" bit 6 pelwu : pe2, pe0 pins wake-up control 0: disable 1: enable note that the pe1 pin has no wake-up function.
rev. 1.10 8? ??ne 10? ?01? rev. 1.10 8 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 5 pdhwu : pd7~pd4 pins wake-up control 0: disable 1: enable bit 4 pdlwu : pd3~pd0 pins wake-up control 0: disable 1: enable bit 3~2 "": unimplemented, read as "0" bit 1 pbhwu : pb6~pb4 pins wake-up control 0: disable 1: enable bit 0 pblwu : pb3~pb0 pins wake-up control 0: disable 1: enable ? ht68fb560 bit 7 6 5 4 3 2 1 0 name pehwu pelwu pdhwu pdlwu pchwu pclwu pbhwu pblwu r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pehwu : pe5~pe4 pins wake-up control 0: disable 1: enable bit 6 pelwu : pe3~pe2, pe0 pins wake-up control 0: disable 1: enable note that the pe1 pin has no wake-up function. bit 5 pdhwu : pd7~pd4 pins wake-up control 0: disable 1: enable bit 4 pdlwu : pd3~pd0 pins wake-up control 0: disable 1: enable bit 3 pchwu : pc7~pc4 pins wake-up control 0: disable 1: enable bit 2 pclwu : pc3~pc0 pins wake-up control 0: disable 1: enable bit 1 pbhwu : pb7~pb4 pins wake-up control 0: disable 1: enable bit 0 pblwu : pb3~pb0 pins wake-up control 0: disable 1: enable port a wake-up polarity control register 7kh,2sruw3fdqehvhwxswrkdyhdfkrlfhrizdnhxssrodulwxvlqjvshflfuhjlvwhu each pin on port a can be selected individ ? ally to have this wake- ? p polarity feat ? re ? sing the padir register.
rev. 1.10 84 ?? ne 10 ? ? 01 ? rev. 1.10 85 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi padir register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 padir : pa7~pa0 pins wake-up edge control 0: rising edge 1: falling edge i/o port control registers each i/o port has it s own cont rol regi ster known as pac~pe c, to cont rol the input /output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pbc register ? HT68FB540/ht68fb550 bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 ? ht68fb560 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pcc register ? ht68fb560 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1
rev. 1.10 84 ??ne 10? ?01? rev. 1.10 85 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi pdc register ? ht68fb550/ht68fb560 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pec register ? HT68FB540/ht68fb550 bit 7 6 5 4 3 2 1 0 name d ? d1 d0 r/w r/w r/w r/w por 1 1 1 ? ht68fb560 bit 7 6 5 4 3 2 1 0 name d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 "": unimplemented, read as "0" bit 5~0 pec : i/o port bit 5~bit 0 input/output control 0: output 1: i nput port a , port d power source control registers port a and port d can be setup to have a choice of various power source using specifc registers. each pin on port a and port d [7:4] ca n be sel ected indivi dually to have vari ous power source s using the paps0, paps1 and pdps registers. paps0 register bit 7 6 5 4 3 2 1 0 name pa ? s1 pa ? s0 pa ? s1 pa ? s0 pa1s1 pa1s0 pa0s1 pa0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pa3s1, pa3s0 : pa3 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 5~4 pa2s1, pa2s0 : pa2 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 3~2 pa1s1, pa1s0 : pa1 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 1~0 pa0s1, pa0s0 : pa0 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output
rev. 1.10 86 ?? ne 10 ? ? 01 ? rev. 1.10 87 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi paps1 register bit 7 6 5 4 3 2 1 0 name pa7s1 pa7s0 pa6s1 pa6s0 pa5s1 pa5s0 pa4s1 pa4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pa7s1, pa7s0 : pa7 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 5~4 pa6s1, pa6s0 : pa6 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 3~2 pa5s1, pa5s0 : pa5 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 1~0 pa4s1, pa4s0 : pa4 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output pdps register ? ht68fb550/ht68fb560 bit 7 6 5 4 3 2 1 0 name pd7s1 pd7s0 pd6s1 pd6s0 pd5s1 pd5s0 pd4s1 pd4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pd7s1, pd7s0 : pd7 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 5~4 pd6s1, pd6s0 : pd6 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 3~2 pd5s1, pd5s0 : pd5 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output bit 1~0 pd4s1, pd4s0 : pd4 power supply control 00: vdd 01: vdd 10: vddio 11: v33o, 3.3v regulator output
rev. 1.10 86 ??ne 10? ?01? rev. 1.10 87 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the le vel of whic h depe nds on the othe r conne cted ci rcuitry and whet her pull -high selections have been chosen. if the port control registers, pac~pec, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa~pe, are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. all ports provide the wake-up function which can be set by individual pin in the port a while it has to be set by nibble pins in the port b, port c, port d and port e. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a voltage level transition on any of the port pins. single or multiple pins on ports can be setup to have this function.

?? ? ? ? ? generic input/output structure
rev. 1.10 88 ?? ne 10 ? ? 01 ? rev. 1.10 89 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions each device includes several timer modules, abbreviated to the nam e tm. the tms are mul ti-purpose ti ming uni ts and serve to provi de operations such as timer/counter , input capture, compare match output and single pulse output as well as bei ng the func tional unit for the gene ration of pwm signa ls. ea ch of the tms has two individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact and standard tm sections. introduction the devices con ta in four tms h aving a reference nam e of tm0, tm1, tm2 and tm3. ea ch individual tm can be categorised as a certain type, namely compact type tm or standard type tm. although sim ilar in na ture, th e di fferent tm ty pes va ry in th eir fe ature co mplexity. the common features to all of the compact and standard tms will be described in this section. the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the two types of tms are summarised in the accompanying table. function ctm stm timer/co ? nter i/p capt ? re compare match o ? tp ? t pwm channels 1 1 single p ? lse o ? tp ? t 1 pwm alignment edge edge pwm adj ? stment period & d ? ty d ? ty or period d ? ty or period tm function summary each device in the series contains a specifc number of either compact type and standard type tm units which are shown in the table together with their individual reference name, tm0~tm3. device tm0 tm1 tm2 tm3 HT68FB540/ht68fb550/ht68fb560 16-bit stm 10-bit stm 10-bit ctm 10-bit ctm tm name/type reference tm operation the different ty pes of tm of fer a di verse ra nge of fun ctions, fro m sim ple ti ming ope rations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running count er whose val ue is the n com pared wit h the val ue of pre-progra mmed int ernal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a com pare ma tch sit uation, a tm int errupt signa l wil l be gen erated whic h ca n cl ear the counter and perh aps al so cha nge the con dition of the tm out put pin . the int ernal tm coun ter is driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.10 88 ??ne 10? ?01? rev. 1.10 89 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi tm clock source the clock sou rce whi ch dr ives th e ma in co unter in ea ch tm ca n or iginate fr om va rious sou rces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f l clock source or the external tckn pin. note that setting these bits to the value 101 will select an undefned clock input, in effect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected usi ng th e tn ck2~tnck0 bi ts. th e tm in put pi n ca n be ch osen to ha ve ei ther a rising or falling active edge. the tms each have two output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and device is different, the details are provided in the accompanying table. all tm output pin names have a "_n" suffx. pin names that include a "_0" or "_1" suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm registers HT68FB540 ht68fb550 ht68fb560 tp ? _0 ? tp ? _1 tp ? _0 ? tp ? _1 tp0_0 ? tp0_1 tp1_0 ? tp1_1 tmpc0 ? tmpc1 tm output pins
rev. 1.10 90 ?? ne 10 ? ? 01 ? rev. 1.10 91 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers device bit 7 6 5 4 3 2 1 0 tmpc0 HT68FB540 ht68fb550 ht68fb560 t1cp1 t1cp0 t0cp1 t0cp0 tmpc1 HT68FB540 ht68fb550 ht68fb560 t ? cp1 t ? cp0 t ? cp1 t ? cp0 tm input/output pin control registers list
tm0 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.10 90 ??ne 10? ?01? rev. 1.10 91 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

tm1 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input.

tm2 function pin control block diagram note: the i/o register data bits shown are used for tm output inversion control.
rev. 1.10 9 ? ?? ne 10 ? ? 01 ? rev. 1.10 9? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

tm3 function pin control block diagram note: the i/o register data bits shown are used for tm output inversion control. tmpc0 register bit 7 6 5 4 3 2 1 0 name t1cp1 t1cp0 t0cp1 t0cp0 r/w r r r/w r/w r r r/w r/w por 0 0 0 1 0 0 0 1 bit 7~6 "": unimplemented, read as "0" bit 5 t1cp1 : tp1_1 pin control 0: disable 1: enable bit 4 t1cp0 : tp1_0 pin control 0: disable 1: enable bit 3~2 "": unimplemented, read as "0" bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable
rev. 1.10 9? ??ne 10? ?01? rev. 1.10 9 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi tmpc1 register bit 7 6 5 4 3 2 1 0 name t ? cp1 t ? cp0 t ? cp1 t ? cp0 r/w r r r/w r/w r r r/w r/w por 0 0 0 1 0 0 0 1 bit 7~6 "": unimplemented, read as "0" bit 5 t3cp1 : tp3_1 pin control 0: disable 1: enable bit 4 t3cp0 : tp3_0 pin control 0: disable 1: enable bit 3~2 "": unimplemented, read as "0" bit 1 t2cp1 : tp2_1 pin control 0: disable 1: enable bit 0 t2cp0 : tp2_0 pin control 0: disable 1: enable programming considerations the tm counter registers and the capture/compare ccra register, being either 10-bit or 16- bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer , reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed.

rev. 1.10 94 ?? ne 10 ? ? 01 ? rev. 1.10 95 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi the following steps show the read and write procedures: ? writing data to ccra ? step 1. write data to low byte tmxal C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte tmxah C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra ? step 1. read data from the high byte tmxdh or tmxah C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl or tmxal C this step reads data from the 8-bit buffer. as the ccra register implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way described above, it is recommended to use the "mov" instruction to access the ccra low byte register, named tmxal, using the following access procedures. accessing the ccra low byte register without following these access procedures will result in unpredictable values. compact type tm although the si mplest form of t he t wo tm t ypes, t he com pact tm t ype st ill c ontains t hree ope rating modes, which ar e co mpare mat ch out put, ti mer/event co unter an d pwm out put mo des. th e compact tm can also be control led wit h an exte rnal input pin and can drive two exte rnal output pins. these two external output pins can be the same signal or the inverse signal. ctm name tm no. tm input pin tm output pin HT68FB540 ht68fb550 ht68fb560 10-bit ctm ??? tck ?? tck ? tp ? _0 ? tp ? _1 ? tp ? _0 ? tp ? _1 ?
? ? ? ? ? ? ? ? ? ?
? ?
? ?

? ? ?
? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ??? ?? compact type tm block diagram
rev. 1.10 94 ??ne 10? ?01? rev. 1.10 95 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are al so two int ernal com parators wit h the nam es, compa rator a and compa rator p. these comparators wil l co mpare th e va lue in th e co unter wit h cc rp an d cc ra re gisters. th e ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the applicat ion program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. compact type tm register description overall operati on of the compact tm is cont rolled using six regist ers. a read only regist er pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d5 d4 d ? d ? d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d4 d ? d ? d1 d0 tmnah d9 d8 compact tm register list (n=2,3) tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 "": unimplemented, read as "0" bit 1~0 tmndh : tmn counter high byte register bit 1~bit 0 tmn 10-bit counter bit 9~bit 8
rev. 1.10 96 ?? ne 10 ? ? 01 ? rev. 1.10 97 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 "": unimplemented, read as "0" bit 1~0 tmnah : tmn ccra high byte register bit 1~bit 0 tmn 10-bit ccra bit 9~bit 8 tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f l 101: undefned 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tmn. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f l are other internal c locks, the details of which can be found in the oscillator section.
rev. 1.10 96 ??ne 10? ?01? rev. 1.10 97 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 3 tnon : tmn counter on/of f control 0: off 1: on this bit controls the overall on/off function of the tmn. setting the bit high enables the counter to run, clearing the bit disables the tmn. clearing this bit to zero will stop the counter from counting and turn off the tmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tmn is in the compare match output mode then the tmn output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register , compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overfow at its maximum value. tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1 ~ tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused
rev. 1.10 98 ?? ne 10 ? ? 01 ? rev. 1.10 99 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi these two bits are used to determine how the tmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tmn is running. in the compare match output mode, the tnio1 and tnio0 bits determine how the tmn output pin cha nges sta te when a com pare ma tch occ urs from t he com parator a. the tmn out put pi n c an be se tup t o swi tch hi gh, swi tch l ow or to toggle its pres ent s tate w hen a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tmn output pin should be setup using the tnoc bit in the tmnc1 register. note that the output le vel re quested by th e tn io1 an d tn io0 bi ts mu st be di fferent fr om the initial value setup using the tnoc bit otherwise no change will occur on the tmn output pin when a compare match occurs. after the tmn output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is mo dified by ch anging th ese two bi ts. it is necessary to only change the value s of the tnio1 and tnio0 bit s only after the tmn has been switched off. un predictable pw m out put s will oc cur if the tnio1 a nd tnio0 bi ts a re c hanged whe n the tm is running. bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tmn output pin. its operation depends upon whether tmn is being used in the compare match output mode or in the pwm mode. it has no effect if the tmn is in the timer/counter mode. in the compare match output mode it determines the logic level of the tmn output pin before a compare match occurs. in the pwm mode it dete rmines if the pwm signal is act ive high or active low. bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tmn output pin will be inverted and not inverted when the bit is zero. it has no effect if the tmn is in the timer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit determines whi ch of th e cc ra an d cc rp re gisters ar e use d fo r pe riod an d duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bit is used to sel ect the me thod whic h cl ears the co unter. rem ember tha t the compact tmn con tains two com parators, com parator a and com parator p, ei ther of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode.
rev. 1.10 98 ??ne 10? ?01? rev. 1.10 99 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or ti mer/counter mod e. th e op erating mo de is sel ected usi ng th e tn m1 an d tn m0 bits in the tmnc1 register . compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to "00" respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare ma tch oc curs fro m com parator p, th e ot her is whe n th e ccr p bi ts ar e al l ze ro whi ch allows the counter to overfow. here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively , will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches i ts maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is generated aft er a com pare ma tch occ urs from com parator a. the tnpf int errupt reque st fla g, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in whi ch th e tm ou tput pi n ch anges sta te ar e de termined by th e co ndition of th e tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from compa rator a. the ini tial condi tion of the tm output pin, whic h is set up aft er the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.10 100 ?? ne 10 ? ? 01 ? rev. 1.10 101 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi co?nter val?e 0x?ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccrp=0 ccrp > 0 co?nter overflow ccrp > 0 co?nter cleared by ccrp val?e pa?se res?me stop co?nter restart tncclr = 0; tnm [1:0] = 00 o?tp?t pin set to initial level low if tnoc=0 o?tp?t toggle with tnaf flag note tnio [1:0] = 10 active high o?tp?t select here tnio [1:0] = 11 toggle o?tp?t select o?tp?t not affected by tnaf flag. remains high ?ntil reset by tnon bit o?tp?t pin reset to initial val?e o?tp?t controlled by other pin-shared f?nction o?tp?t inverts when tnpol is high compare match output mode C tncclr= 0 note: 1. with tncclr= 0 , a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the o utput pin is reset to its initial state by a tnon bit rising edge
rev. 1.10 100 ??ne 10? ?01? rev. 1.10 101 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi co?nter val?e 0x?ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 co?nter overflow ccra > 0 co?nter cleared by ccra val?e pa?se res?me stop co?nter restart tncclr = 1; tnm [1:0] = 00 o?tp?t pin set to initial level low if tnoc=0 o?tp?t toggle with tnaf flag note tnio [1:0] = 10 active high o?tp?t select here tnio [1:0] = 11 toggle o?tp?t select o?tp?t not affected by tnaf flag. remains high ?ntil reset by tnon bit o?tp?t pin reset to initial val?e o?tp?t controlled by other pin-shared f?nction o?tp?t inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow o?tp?t does not change compare match output mode C tncclr= 1 note: 1. with tncclr= 1 , a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the o utput pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr= 1 timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/c ounter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function.
rev. 1.10 10 ? ?? ne 10 ? ? 01 ? rev. 1.10 10? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating co ntrol, il lumination co ntrol et c. by pr oviding a sig nal of fi xed fre quency bu t of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is ext remely fle xible. in the pwm mode , the tncclr bit has no ef fect on the pwm operation. both of the ccra and ccrp regi sters are used to generat e the pwm waveform , one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm mode, edge-aligned mode, tndpx= 0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 d ? ty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra = 128, the ctm pwm output frequency = (f sys /4)/512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, tndpx= 1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra d ? ty 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 the pwm ou tput pe riod is de termined by th e cc ra re gister va lue to gether wit h th e tm cl ock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.10 10? ??ne 10? ?01? rev. 1.10 10 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi co?nter val?e ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time co?nter cleared by ccrp pa?se res?me co?nter stop if tnon bit low co?nter reset when tnon ret?rns high tndpx = 0; tnm [1:0] = 10 pwm d?ty cycle set by ccra pwm res?mes operation o?tp?t controlled by other pin-shared f?nction o?tp?t inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) pwm mode C tndpx= 0 note: 1. here tndpx= 0 C counter cleared by ccrp 2. a c ounter clear sets the pwm period 3. the i nternal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.10 104 ?? ne 10 ? ? 01 ? rev. 1.10 105 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi co?nter val?e ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time co?nter cleared by ccra pa?se res?me co?nter stop if tnon bit low co?nter reset when tnon ret?rns high tndpx = 1; tnm [1:0] = 10 pwm d?ty cycle set by ccrp pwm res?mes operation o?tp?t controlled by other pin-shared f?nction o?tp?t inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) pwm mode C tndpx= 1 note: 1. here tndpx = 1 C counter cleared by ccra 2. a c ounter clear sets the pwm period 3. the i nternal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.10 104 ??ne 10? ?01? rev. 1.10 105 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi standard type tm C stm the standard type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one or two external output pins. stm name tm no. tm input pin tm output pin HT68FB540 ht68fb550 ht68fb560 16-bit stm 10-bit stm 0 ? 1 tck0 ? tck1 tp0_0 ? tp0_1 tp1_0 ? tp1_1 standard tm operation there are two sizes of standard tms, one is 10-bit wide and the other is 16-bit wide. at the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the ccra is the ten or sixteen bits and therefore compares all counter bits. the only way of ch anging th e va lue of th e 10 or 16- bit co unter usi ng th e ap plication pro gram, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
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rev. 1.10 106 ?? ne 10 ? ? 01 ? rev. 1.10 107 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits. 16-bit standard tm register list name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm0c0 t0pau t0ck ? t0ck1 t0ck0 t0on tm0c1 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0px t0clr tm0dl d7 d6 d5 d4 d ? d ? d1 d0 tm0dh d15 d14 d1 ? d1 ? d11 d10 d9 d8 tm0al d7 d6 d5 d4 d ? d ? d1 d0 tm0ah d15 d14 d1 ? d1 ? d11 d10 d9 d8 tm0rp d7 d6 d5 d4 d ? d ? d1 d0 ? tm0c0 register bit 7 6 5 4 3 2 1 0 name t0pau t0ck ? t0ck1 t0ck0 t0on r/w r/w r/w r/w r/w r/w r r r por 0 0 0 0 0 0 0 0 bit 7 t0pau : tm0 counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t0ck2, t0ck1, t0ck0 : select tm0 counter clock 000: f sys/ 4 001: f sys 010: f h /16 011: f h /64 100: f l 101: reserved 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, whi le f h and f l are other internal cl ocks, th e de tails of whi ch ca n be found in the oscillator section.
rev. 1.10 106 ??ne 10? ?01? rev. 1.10 107 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 3 t0on : tm0 counter on/of f control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t0oc bit, when the t0on bit changes from low to high. bit 2~0 "": unimplemented, read as "0" ? tm0c1 register bit 7 6 5 4 3 2 1 0 name t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t0m1~t0m0 : select tm0 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t0m1 and t0m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t0io1~t0io0 : select tp0_0, tp0_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/ single pulse output mode 00: force inactive state 01: force active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp0_0, tp0_1 01: input capture at falling edge of tp0_0, tp0_1 10: input capture at falling/rising edge of tp0_0, tp0_1 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is rea ched. the funct ion tha t the se bit s sel ect depe nds upon in whic h mode the tm is running. in the compare match output mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t0oc bit in the tm0c1 register. note that the output level requested by the t0io1 and t0io0 bits must be different from the initial value setup using the t0oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t0on bit from low to high.
rev. 1.10 108 ?? ne 10 ? ? 01 ? rev. 1.10 109 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi in the pwm mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the value s of the t0io1 and t0io0 bits only after the tm has been switched off. u npredictable pw m out put s will oc cur if the t0io1 a nd t0io0 bi ts a re c hanged whe n the tm is running. bit 3 t0oc : tp0_0, tp0_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare mat ch outpu t mode it det ermines the log ic le vel of the tm out put pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t0pol : tp0_0, tp0_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp0_0 or tp0_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t0dpx : tm0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t0cclr : select tm0 counter clear condition 0: tm0 comparator p match 1: tm0 comparator a match this bit is used to sel ect the me thod whic h cl ears the co unter. rem ember tha t the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t0 cclr bi t is no t used in the pwm, single pulse or input capture mode. ? tm0dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm0dl : tm0 counter low byte register bit 7~bit 0 tm0 16-bit counter bit 7~bit 0
rev. 1.10 108 ??ne 10? ?01? rev. 1.10 109 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? tm0dh register bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm0dh : tm0 counter high byte register bit 7~bit 0 tm0 16-bit counter bit 15~bit 8 ? tm0al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0al : tm0 ccra low byte register bit 7~bit 0 tm0 16-bit ccra bit 7~bit 0 ? tm0ah register bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0ah : tm0 ccra high byte register bit 7~bit 0 tm0 16-bit ccra bit 15~bit 8 ? tm0rp register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0rp : tm0 ccrp register bit 7~bit 0 tm0 ccrp 8-bit register , compared with the tm0 counter bit 15~bit 8. comparator p match period 0: 65536 tm0 clocks 1~255: 256 x (1~255) tm0 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counter s highest eight bits. the result of this comparison ca n be sel ected to cl ear the int ernal count er if the t0c clr bit is set to zero. setting the t0ccl r bit to zero ensure s tha t a com pare mat ch wit h the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all ei ght bit s to ze ro is in ef fect al lowing the count er to overflow at it s maximum value. 10-bit standard tm register list name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 tm1c1 t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr tm1dl d7 d6 d5 d4 d ? d ? d1 d0 tm1dh d9 d8 tm1al d7 d6 d5 d4 d ? d ? d1 d0 tm1ah d9 d8
rev. 1.10 110 ?? ne 10 ? ? 01 ? rev. 1.10 111 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? tm1c0 register bit 7 6 5 4 3 2 1 0 name t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the counter ca n be pause d by set ting thi s bit high. cle aring the bit to ze ro rest ores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f l 101: undefned 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, whi le f h and f l are other internal cl ocks, th e de tails of whi ch ca n be found in the oscillator section. bit 3 t1on : tm1 counter on/of f control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to ru n, cl earing th e bi t di sables th e tm. cl earing th is bi t to ze ro wil l stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tmn ccrp 3-bit register , compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overfow at its maximum value.
rev. 1.10 110 ??ne 10? ?01? rev. 1.10 111 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? tm1c1 register bit 7 6 5 4 3 2 1 0 name t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1m1~t1m0 : select tm1 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1m1 and t1m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1io1~t1io0 : select tp1_0, tp1_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1_0, tp1_1 01: input capture at falling edge of tp1_0, tp1_1 10: input capture at falling/rising edge of tp1_0, tp1_1 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare mat ch output mode, the t1io1 and t1io0 bit s det ermine how the tm output pin changes state when a compare match occurs from the comparat or a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1oc bit in the tm1c1 register. note that the output level requested by the t1io1 and t1io0 bits must be different from the initial value setup using the t1oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the value s of the t1io1 and t1io0 bits only after the tm has been switched off. u npredictable pw m out put s will oc cur if the t1io1 a nd t1io0 bi ts a re c hanged whe n the tm is running
rev. 1.10 11 ? ?? ne 10 ? ? 01 ? rev. 1.10 11 ? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 3 t1oc : tp1_0, tp1_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare mat ch outpu t mode it det ermines the log ic le vel of the tm out put pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1pol : tp1_0, tp1_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1_0 or tp1_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1dpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to sel ect the me thod whic h cl ears the co unter. rem ember tha t the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode. ? tm1dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 ? tm1dh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 "": unimplemented, read as "0" bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8
rev. 1.10 11 ? ??ne 10? ?01? rev. 1.10 11 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? tm1al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al : tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 ? tm1ah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 "": unimplemented, read as "0" bit 1~0 t m1ah : tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 standard type tm operating modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register . compare output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare ma tch fro m com parator p, th e ot her is whe n th e cc rp bi ts ar e al l ze ro whi ch al lows the counter to overfow . here both tnaf and tnpf int errupt reque st fags for compa rator a and comparator p respectively , will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is hi gh no tn pf in terrupt re quest fag wil l be ge nerated. in th e co mpare mat ch out put mode, the ccra can not be set to "0". as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is generated aft er a com pare ma tch occ urs from com parator a. the tnpf int errupt reque st fla g, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in whi ch th e tm ou tput pi n ch anges sta te ar e de termined by th e co ndition of th e tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from compa rator a. the ini tial condi tion of the tm output pin, whic h is set up aft er the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.10 114 ?? ne 10 ? ? 01 ? rev. 1.10 115 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/c ounter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. co?nter val?e 0x?ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccrp=0 ccrp > 0 co?nter overflow ccrp > 0 co?nter cleared by ccrp val?e pa?se res?me stop co?nter restart tncclr = 0; tnm [1:0] = 00 o?tp?t pin set to initial level low if tnoc=0 o?tp?t toggle with tnaf flag note tnio [1:0] = 10 active high o?tp?t select here tnio [1:0] = 11 toggle o?tp?t select o?tp?t not affected by tnaf flag. remains high ?ntil reset by tnon bit o?tp?t pin reset to initial val?e o?tp?t controlled by other pin-shared f?nction o?tp?t inverts when tnpol is high compare match output mode C tncclr= 0 note: 1. with tncclr= 0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the o utput pin is reset to its initial state by a tnon bit rising edge
rev. 1.10 114 ??ne 10? ?01? rev. 1.10 115 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi co?nter val?e 0x?ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 co?nter overflow ccra > 0 co?nter cleared by ccra val?e pa?se res?me stop co?nter restart tncclr = 1; tnm [1:0] = 00 o?tp?t pin set to initial level low if tnoc=0 o?tp?t toggle with tnaf flag note tnio [1:0] = 10 active high o?tp?t select here tnio [1:0] = 11 toggle o?tp?t select o?tp?t not affected by tnaf flag. remains high ?ntil reset by tnon bit o?tp?t pin reset to initial val?e o?tp?t controlled by other pin-shared f?nction o?tp?t inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow o?tp?t does not change compare match output mode C tncclr= 1 note: 1. with tncclr= 1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the o utput pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr= 1 timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/c ounter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 registe r should be set to 10 respect ively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values.
rev. 1.10 116 ?? ne 10 ? ? 01 ? rev. 1.10 117 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is ext remely fle xible. in the pwm mode , the tnccl r bit has no ef fect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. 16-bit stm, pwm mode, edge-aligned mode, t0dpx= 0 ccrp 1~255 000b period ccrp x ? 56 655 ? 6 d ? ty ccra if f sys = 16mhz, tm clock source select f sys /4, ccrp = 2 and ccra = 128, the stm pwm output frequency = (f sys /4)/(2x256)= f sys /2048 = 7.8125khz, duty= 128/512= 25% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 16-bit stm, pwm mode, edge-aligned mode, t0dpx= 1 ccrp 1~255 000b period ccra d ? ty ccrp x ? 56 655 ? 6 the pw m o utput pe riod i s de termined by t he c cra re gister va lue t ogether wit h t he tm c lock whi le the pwm duty cycle is defned by the (ccrp x 256) except when ccrp value is equal to 000b. 10-bit stm, pwm mode, edge-aligned mode, t1dpx= 0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 d ? ty ccra if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b and ccra = 128, the stm pwm output frequency = (f sys /4)/512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit stm, pwm mode, edge-aligned mode, t1dpx= 1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra d ? ty 1 ? 8 ? 56 ? 84 51 ? 640 768 896 10 ? 4 the pwm ou tput pe riod is de termined by th e cc ra re gister va lue to gether wit h th e tm cl ock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.10 116 ??ne 10? ?01? rev. 1.10 117 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi co?nter val?e ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time co?nter cleared by ccrp pa?se res?me co?nter stop if tnon bit low co?nter reset when tnon ret?rns high tndpx = 0; tnm [1:0] = 10 pwm d?ty cycle set by ccra pwm res?mes operation o?tp?t controlled by other pin-shared f?nction o?tp?t inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) pwm mode C tndpx= 0 note: 1. here tndpx= 0 C counter cleared by ccrp 2. a c ounter c lear sets the pwm period 3. the i nternal pwm function continues running even when tnio [1:0]= 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.10 118 ?? ne 10 ? ? 01 ? rev. 1.10 119 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi co?nter val?e ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time co?nter cleared by ccra pa?se res?me co?nter stop if tnon bit low co?nter reset when tnon ret?rns high tndpx = 1; tnm [1:0] = 10 pwm d?ty cycle set by ccrp pwm res?mes operation o?tp?t controlled by other pin-shared f?nction o?tp?t inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) pwm mode C tndpx= 1 note: 1. here tndpx= 1 C counter cleared by ccra 2. a c ounter clear sets the pwm period 3. the i nternal pwm function continues even when tnio [1:0]= 00 or 01 4. the tncclr bit has no infuence on pwm operation single pulse mode to select this mode, bits tnm1 and tnm0 in the tmnc1 registe r should be set to 10 respect ively and also the tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control
rev. 1.10 118 ??ne 10? ?01? rev. 1.10 119 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode.

? ? ? ? ? ?? ? ? ?? single pulse generation co?nter val?e ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time co?nter stopped by ccra pa?se res?me co?nter stops by software co?nter reset when tnon ret?rns high tnm [1:0] = 10 ; tnio [1:0] = 11 p?lse width set by ccra o?tp?t inverts when tnpol = 1 no ccrp interr?pts generated tm o/p pin (tnoc=0) tckn pin software trigger cleared by ccra match tckn pin trigger a?to. set by tckn pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the p ulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit hight 5. in the single pulse mode, tnio [1:0] must be set to "1 1" and can not be changed.
rev. 1.10 1 ? 0 ?? ne 10 ? ? 01 ? rev. 1.10 1?1 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively . this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpn_0 or tpn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register . the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0 or tpn_1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tpn_0 or tpn_1 pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of ove rflow int errupt sig nals from the ccrp ca n be a useful me thod in me asuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn_0 or tpn_1 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0 or tpn_1 pin, however it must be noted that the counter will continue to run. as the tpn_0 or tpn_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr and tndpx bits are not used in this mode.
rev. 1.10 1?0 ??ne 10? ?01? rev. 1.10 1 ? 1 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi co?nter val?e yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra val?e time co?nter cleared by ccrp pa?se res?me co?nter reset tnm [1:0] = 01 tm capt?re pin tpn_x xx co?nter stop tnio [1:0] val?e xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disable capt?re capture input mode note: 1. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.10 122 june 10, 2013 rev. 1.10 123 june 10, 2013 HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi serial interface module C sim the devices contain a serial interface module, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim interface function must frst be selected by software control. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o are selected using pull-high control registers, and also if the sim function is enabled. there is one control register associated with the serial interface control, namely sbsc. this is used to enable the sim_wcol bit function, sa_wcol bit function and i 2 c debounce selection. the devices provide two kinds of spi function, namely spi and spia, each of them has the corresponding wcol control bits to enable the sim wcol and spia wcol control bits, namely sim_wcol and sa_wcol respectively. in addition, the i2cdb1 and i2cdb0 bits are used to select the i 2 c debounce time. spi interface this spi interface function , which is part of the serial interface module , should not be confused with the other independent spi function, known as spia, which is described in another section of this datasheet. the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spi interface specifcation can control multiple slave devices from a single master, but this device provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data ou tput lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin- shared with other functions and with the i 2 c function pins, the spi interface must frst be selected by the correct bits in the simc0 and simc2 registers. after the spi option has been selected, it can also be additionally disabled or enabled using the simen bit in the simc0 register. spi master/slave connection
rev. 1.10 1?? ??ne 10? ?01? rev. 1.10 1 ?? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

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?? ? ? ? ? - ? ? ? ? ? ? ? ? ? ??? ? ? ? ? spi block diagram the spi function in these devices offer the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? wcol bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. spi registers there are four internal registers which control the overall operation of the spi interface. these are the simd data register and three registers simc0, simc2 and sbsc. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcken pckp1 pckp0 simen simd d7 d6 d5 d4 d ? d ? d1 d0 simc ? d7 d6 ckpolb ckeg mls csen wcol trf sbsc sim_wcol i ? cdb1 i ? cdb0 sa_wcol sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi an d i 2 c functions. before th e de vice wri tes da ta to th e spi bu s, th e ac tual da ta to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. the sim_wcol bit in the sbsc register is used to control the spi wcol function.
rev. 1.10 1 ? 4 ?? ne 10 ? ? 01 ? rev. 1.10 1?5 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" ? nknown there are also three control registers for the spi interface, simc0 simc2 and sbsc. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/ disable function and to set the data transmission clock frequency. although not connected with the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc. simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w r por 1 1 1 0 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f l 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from f l or tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2
rev. 1.10 1?4 ??ne 10? ?01? rev. 1.10 1 ? 5 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs, or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be frst initialised by the appl ication program whil e the rel evant i 2 c fags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 "": unimplemented, read as "0" simc2 register bit 7 6 5 4 3 2 1 0 name d7 d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bit this bit can be read or written by the application program . bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck li ne wil l be low when the cl ock is ina ctive. whe n the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is executed othe rwise an errone ous cl ock edge ma y be gene rated. the ckpolb bit determines the base condi tion of the cl ock li ne, if the bit is high, the n the sck li ne will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst.
rev. 1.10 1 ? 6 ?? ne 10 ? ? 01 ? rev. 1.10 1?7 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and placed into i/o pin or the other functions. if the bit is high the scs pin will be enabled and used as a select pin. bit 1 wcol : spi write collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcol bit can be disabled or enabled via the sim_wcol bit in the sbsc register . bit 0 trf : spi transmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receiv e complete fag and is set "1" automatically when an spi data transmission is completed, but must set to "0" by the application program. it can be used to generate an interrupt. sbsc register bit 7 6 5 4 3 2 1 0 name sim_wcol i ? cdb1 i ? cdb0 sa_wcol r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 sim_wcol : sim wcol control bit 0: disable 1: enable bit 6 "": unimplemented, read as "0" bit 5~4 i2cdb1, i2cdb0 : i 2 c debounce selection bits related to i 2 c function, described elsewhere bit 3~1 "": unimplemented, read as "0" bit 0 sa_wcol : spia wcol function control related to spia function, described elsewhere spi communication after the spi int erface is ena bled by set ting the simen bit high, then in the mast er mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is com plete, the trf fla g wil l be set aut omatically, but must be cl eared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
rev. 1.10 1?6 ??ne 10? ?01? rev. 1.10 1 ? 7 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi
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rev. 1.10 1 ? 8 ?? ne 10 ? ? 01 ? rev. 1.10 1?9 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

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? ? ? ? ? ? -? ?? ? ? ? ? ? ? ???? ??? ? ????? ?? ?? ? ???? ? spi transfer control flowchart spi bus enable/disable to enable the spi bus, set csen= 1 and scs = 0, then wait for data to be written into the simd (txrx buffer) regi ster. for the mast er mode, aft er dat a has bee n writ ten to the simd (txrx buffer) register, then transmission or reception will start automatically. when all the data has been transferred, the trf bit should be set. for the slave mode, when clock pulses are received on sck, data in the txrx buffer will be shifted out or data on sdi will be shifted in.to disable the spi bus, the sck, sdi, sdo and scs will become i/o pins or the other functions.
rev. 1.10 1?8 ??ne 10? ?01? rev. 1.10 1 ? 9 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi spi operation all communication is carried out using the 4-line interface for either master or slave mode.the csen bit in the simc2 register controls the overall function of the spi interface. setting this bit high will enable the spi int erface by al lowing the scs line to be ac tive, whic h ca n the n be used to control the spi interface. if the csen bit is low, the spi interface will be disabled and the scs line will be an i/o pin or the othe r funct ions and ca n the refore not be used for con trol of the spi interface. if the csen bit and the simen bit in the simc0 are set high, this will place the sdi line in a foating condition and the sdo line high. if in master mode the sck line will be either high or low depending upon the clock polarity selection bit ckpolb in the simc2 register. if in slave mode the sck line will be in a foating condition. if the simen bit is low, then the bus will be disabled and scs , sdi, sdo and sck will all become i/o pins or the other functions. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the simd register. in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode: master mode ? step 1 select the spi master mode and clock source using the sim2~sim0 bits in the simc0 control register ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the slave device. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register, which will actually place the data into the txrx buf fer. then use the sck and scs lines to output the data. after this, go to step5. for read operations: th e da ta tr ansferred in on th e sdi li ne wil l be sto red in th e txr x bu ffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register. ? step 8 clear trf. ? step 9 go to step 4.
rev. 1.10 1 ? 0 ?? ne 10 ? ? 01 ? rev. 1.10 1?1 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi slave mode ? step 1 select the spi slave mode using the sim2~sim0 bits in the simc0 control register ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the master device. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register, which will actually place the data into the txrx buf fer. then wait for the master clock sck and scs signal. after this, go to step5. for read operations: th e da ta tr ansferred in on th e sdi li ne wil l be sto red in th e txr x bu ffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register. ? step 8 clear trf. ? step 9 go to step 4. error detection the wcol bit in the simc2 register is provided to indicate errors during data transfer. the bit is set by the spi serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the simd register takes place during a data transfer operation and will prevent the write operation from continuing. the overall function of the wcol bit can be disabled or enabled by the sim_wcol bit in the sbsc register. . i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom me mory et c. ori ginally de veloped by phi lips, it is a two li ne lo w spe ed ser ial in terface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection
rev. 1.10 1?0 ??ne 10? ?01? rev. 1.10 1 ? 1 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the sla ve devi ce. both ma ster and sla ve ca n tra nsmit and rec eive dat a, however, it is the master device that has overall control of the bus. for these devices, which only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. the debounce time of the i 2 c interface can be determined by the i2cdb1 and i2cdb0 bits in the sbsc register. this uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks.
i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sbsc, one address register sima and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. the i2cdb0 and i2cdb1 in the sbsc register are used to select the i 2 c debounce time.
rev. 1.10 1 ?? ?? ne 10 ? ? 01 ? rev. 1.10 1?? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 pcken pckp1 pckp0 simen simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d6 d5 d4 d ? d ? d1 d0 sima iica6 iica5 iica4 iica ? iica ? iica1 iica0 d0 sbsc sim_wcol i ? cdb1 i ? cdb0 sa_wcol i 2 c registers list ? simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w r por 1 1 1 0 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f l 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the f l or tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs, or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is confgured to opera te as an spi int erface via sim2~sim0 bit s, the cont ents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htxand txak wil l rem ain at the prev ious set tings and shoul d the refore be frst initialised by the appl ication program whil e the rel evant i 2 c fags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 "": unimplemented, read as "0".
rev. 1.10 1?? ??ne 10? ?01? rev. 1.10 1 ?? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? simc1 register bit 7 6 5 4 3 2 1 0 name hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus address match fag 0: not address match 1: address match the hass fag is the address mat ch fag. this fag is used to dete rmine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb fa g i s t he i 2 c busy fag. thi s fag wi ll be "1" whe n t he i 2 c bus is busy which will occur when a star t signal is detected. the fag will be set to "0" when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data,this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is th e i 2 c slave read/write fl ag. th is fl ag de termines whe ther the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the srw fag to determine whether it should be in transmit mode or receive mode. if the srw fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i 2 c address match wake-up control 0: disable 1: enable this bit should be set to "1" to enable i 2 c address match wake up from sleep or idle mode.
rev. 1.10 1 ? 4 ?? ne 10 ? ? 01 ? rev. 1.10 1?5 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave does not receive acknowledge fag the rxak fl ag is th e re ceiver ac knowledge fl ag. wh en th e rxak fl ag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. the slave tra nsmitter wil l the refore co ntinue sendi ng out dat a unti l the rxak fag is "1". when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. ? simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" ? nknown ? sima register bit 7 6 5 4 3 2 1 0 name iica6 iica5 iica4 iica ? iica ? iica1 iica0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x 0 "x" ? nknown bit 7~1 iica6~ iica0 : i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6~bit 0. the sima re gister is al so use d by th e spi in terface bu t ha s th e na me simc 2. th e sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register define the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program. ? sbsc register bit 7 6 5 4 3 2 1 0 name sim_wcol i ? cdb1 i ? cdb0 sa_wcol r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 sim_wcol : sim wcol control bit related to spi, described elsewhere. bit 6 "": unimplemented, read as "0"
rev. 1.10 1?4 ??ne 10? ?01? rev. 1.10 1 ? 5 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 5~4 i2cdb1, i2cdb0 : i 2 c debounce selection bits 00: no debounce (default) 01: 1 system clock debounce 10, 11: 2 system clocks debounce bit 3~1 "": unimplemented, read as "0" bit 0 sa_wcol : spia wcol function control related to spia, described elsewhere.

? ? ? ? ? ?-? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? i 2 c block diagram i 2 c bus communication communication on the i 2 c bus requires four separate steps, a star t signal, a slave device address transmission, a data transmission and finally a stop signal. when a star t signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initial ise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and simen bits in the simc0 register to "1" to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima . ? step 3 set the sime interrupt enable bit of the interrupt control register to enable the sim interrupt.
rev. 1.10 1 ? 6 ?? ne 10 ? ? 01 ? rev. 1.10 1?7 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

? ? ? ? ? ?- ?? ? ? ? ?? ? ? ? ? ?- i 2 c bus initialisation flow chart i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this star t signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a star t condition occurs when a high to low transition on the sda line takes place when the scl line remains high. i 2 c bus slave address the transmission of a star t sig nal by th e ma ster wil l be de tected by al l de vices on th e i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the star t signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be exa mined to see whet her the int errupt source has com e from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the sim d register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.10 1?6 ??ne 10? ?01? rev. 1.10 1 ? 7 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi i 2 c bus read/write signal the srw bit in the simc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the master has transmitted a calling address , any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the srw fag to determine if it is to be a transmitter or a receiver. if the srw fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to "1" . if the srw fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to "0" . i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its sla ve ad dress. th e or der of ser ial bi t tr ansmission is th e msb frst an d th e lsb la st. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0"., before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver , the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a st op signal from the master .
rev. 1.10 1 ? 8 ?? ne 10 ? ? 01 ? rev. 1.10 1?9 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi
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- ? ? i 2 c communication timing diagram note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
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i 2 c bus isr flow chart
rev. 1.10 1?8 ??ne 10? ?01? rev. 1.10 1 ? 9 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi i 2 c time out function the i 2 c interface provides a time-out scheme to prevent a locked situation which might take place by an unexpected clock timing generated by a noise input signal. when the i 2 c interface has been locked for a period of time, the i 2 c hardware and the register , simc1, will be initialized automatically and the i2ctof bit in the i2ctoc register will be set high. the time out function enable/disable and the time-out period are managed by the i2ctoc register. i 2 c time out operation the time-out counter will start counting when the i 2 c interface received the star t bit and address match. after that the counter will be cleared on each falling edge of the scl pin. if the time counter is larger than the selected time-out time, then the anti-locked protection scheme will take place and the time-out counter will be stopped by hardware automatically, the i2ctof bit will be set high and an i 2 c interrupt will also take place. note that this scheme can also be stopped when the i 2 c received the stop bit. there are several time-out periods can be selected by the i2ctos0~i2ct os5 bits in the i2ctoc register. ? i2ctoc register bit 7 6 5 4 3 2 1 0 name i ? ctoen i ? ctof i ? ctos5 i ? ctos4 i ? ctos ? i ? ctos ? i ? ctos1 i ? ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 i2ctoen : i 2 c time out function control bit 0: disable 1: enable bit 6 i2ctof : i 2 c time out indication bit 0: not occurred 1: occurred bit 5~0 i2ctos5~i2ctos0 : i 2 c time out time period select the i 2 c time out clock is provided by the f l /32. the time out time peri od can be calculated from the accompanying equation. ([i2ctos5:i2ctos0]+1) x (32/f l ) serial interface C spia the devices contain an independent spi function. it is important not to confuse this independent spi function with the additional one contained within the combined sim function, which is described in another section of this datasheet. this independent spi function will carry the name spia to distinguish it from the other one in the sim. the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spia interface specifcation can control multiple slave devices from a single master, however this device is provided with only one scsa pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pins to select the slave devices.
rev. 1.10 140 ?? ne 10 ? ? 01 ? rev. 1.10 141 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi spia interface operation the spia interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdia, sdoa, scka and scsa . pins sdia and sdoa are the serial data input and serial data output lines, scka is the serial clock line and scsa is the slave select line. as the spia interface pins are pin-shared with normal i/o pins, the spia interface must first be enabled by setting the correct bits in the spiac0 and spiac1 registers. the spia can be disabled or enabled using the spiaen bit in the spiac0 register. communication between devices connected to the spia interface is ca rried ou t in a sla ve/master mod e wit h al l da ta tra nsfer in itiations be ing implemented by the master. the master also controls the clock signal. as the device only contains a single scsa pin only one slave device can be ut ilized. the scsa pin is controlled by the app lication progr am, set the sacsen bit to "1" to ena ble the scsa pin function and clear the sacsen bit to "0" to place the scsa pin into a foating state. spia master/slave connection

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?? ? ? ? ? - ? ? ? ? ? ? ? ? ? ? ??? ? ? ? ? spia block diagram the spia function in this device of fers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? sawcol bit enabled or disable select the status of the spia interface pins is determined by a number of factors such as whether the device i s i n t he m aster o r sl ave m ode a nd upon t he c ondition of c ertain c ontrol bi ts suc h a s sacse n and spiaen.
rev. 1.10 140 ??ne 10? ?01? rev. 1.10 141 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi spia registers there are four internal registers which control the overall operation of the spia interface. these are the spiad data register and three registers spiac0, spiac1 and sbsc. the sa_wcol bit in the sbsc register is used to control the spia wcol function. register name bit 7 6 5 4 3 2 1 0 spiac0 saspi ? saspi1 saspi0 spiaen spiac1 sackpol sackeg samls sacsen sawcol satrf spiad d7 d6 d5 d4 d ? d ? d1 d0 sbsc sim_wcol i ? cdb1 i ? cdb0 sa_wcol spia registers list the spiad register is used to store the data being transmitted and received. before the device writes data to the spia bus, the actual data to be transmitted must be placed in the spiad register. after the data is received from the spia bus, the device can read it from the spiad register. any transmission or reception of data from the spia bus must be made via the spiad register . spiad register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" ? nknown there are also three control registers for the spia interface, spiac0, spiac1 and sbsc. register spiac0 is used to control the enable/disable function and to set the data transmission clock frequency. register spiac1 is used for other control functions such as lsb/msb selection, write collision fag etc. spiac0 register bit 7 6 5 4 3 2 1 0 name saspi ? saspi1 saspi0 spiaen r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 0 bit 7~5 saspi2 ~ saspi0 : master/slave clock select 000 : spia master , f sys /4 001 : spia master , f sys /16 010 : spia master , f sys /64 011 : spia master , f l 100 : spia master , tm0 ccrp match frequency/2 101 : spia slave 110: unimplemented 111: unimplemented these bits are used to control the spia master/slave selection and the spi a master clock frequency. th e spi a clock is a fu nction of th e syst em cl ock bu t ca n al so be chosen to be sourced from tm0. if the spi a slave mode is selected then the clock will be supplied by an external master device bit 4~2 "": unimplemented, read as "0"
rev. 1.10 14 ? ?? ne 10 ? ? 01 ? rev. 1.10 14? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 1 spiaen : spia enable or disable 0: disable 1: enable the bit is the overall on/off control for the sim a interface. when the s pia en bit is cleared to ze ro to disa ble th e spia interface, the sdi a , sdo a , sck a and scsa lines will lose their spi function and the s pia operating current will be reduced to a minimum value. when the bit i s high the spia interface is enabled. bit 0 "": unimplemented, read as "0" spiac1 register bit 7 6 5 4 3 2 1 0 name sackpol sackeg samls sacsen sawcol satrf r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 "": unimplemented, read as "0". this bit can be read or written by user software program. bit 5 sackpol : determines the base condition of the clock line 0: scka line will be high when the clock is inactive 1: scka line will be low when the clock is inactive the sackpol bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpol bit is low, then the scka line will be high when the clock is inactive. bit 4 sackeg : determines the spia scka active clock edge type sackpol= 0: 0: scka has high base level with data capture on scka rising edge 1: scka has high base level with data capture on scka falling edge sackpol= 1: 0: scka has low base level with data capture on scka falling edge 1: scka has low base level with data capture on scka rising edge the sackeg and sackpol bit s are used to set up the way tha t the cl ock signa l outputs and inputs data on the spi bus. these two bits must be confgured before a data transfer is executed otherwise an erroneous clock edge may be generated. the sackpol bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sack pol bit is low, then the scka line will be high when the clock is inactive. the sackeg bit determines active c lock e dge t ype whi ch de pends upon t he c ondition of t he sackpol bit. bit 3 samls : msb/lsb first bit 0: lsb shift frst 1: msb shift frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 sacsen : select signal enable/disable bit 0: disable, other functions 1: enable the sacsen bit is used as an enable/disable for the scsa pin. if this bit is low, then the scsa pin will be disabled and placed into other functions. if the bit is high the scsa pin will be enabled and used as a select pin.
rev. 1.10 14? ??ne 10? ?01? rev. 1.10 14 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 1 sawcol : write collision bit 0: collision free 1: collision detected the sawcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the spiad register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that this function can be disabled or enabled via the sa_wcol bit in the sbsc register . bit 0 satrf : transmit/receive flag 0: not complete 1: transmission/reception complete the satrf bit is the tra nsmit/receive compl ete fla g and is set "1" aut omatically when an spia data transmission is completed, but must set to zero by the application program. it can be used to generate an interrupt. sbsc register bit 7 6 5 4 3 2 1 0 name sim_wcol i ? cdb1 i ? cdb0 sa_wcol r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 sim_wcol : sim wcol control bit related to spi, described elsewhere. bit 6 "": unimplemented, read as "0" bit 5~4 i2cdb1, i2cdb0 : i 2 c debounce selection bits related to i 2 c, described elsewhere. bit 3~1 "": unimplemented, read as "0" bit 0 sa_wcol : spia wcol function control 0: disable 1: enable. spia communication after the spia interface is enabled by setting the spiaen bit high, then in the master mode, when data is written to the spiad register, transmission/reception will begin simultaneously. when the data transfer is com plete, the sat rf fag wil l be set aut omatically, but must be cle ared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the spiad register will be transmitted and any data on the sdia pin will be shifted into the spiad register. the master should output an scsa signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scsa signal depending upon the configurations of the sackpol bit and sackeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the sackpol and sackeg bits. the spia will continue to function even in the idle mode.
rev. 1.10 144 ?? ne 10 ? ? 01 ? rev. 1.10 145 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi
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? spia master mode timing

? ? ? ?? ? ? ? - ? ? spia slave mode timing C sackeg= 0
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?? ??? ? ? ? spia slave mode timing C sackeg= 1
rev. 1.10 144 ??ne 10? ?01? rev. 1.10 145 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi

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? ? ? ? -? ? ? ? ?? ? ? ? ???? ? ??? ????? ?? ?? ?? ?? ? ? spia transfer control flowchart spia bus enable/disable to enable the spia bus, set sacsen= 1 and scsa =0, then wait for data to be written into the spiad (txrx buffer) register. for the master mode, after data has been written to the spiad (txrx buffer) register, then transmission or reception will start automatically. when all the data has been transferred the satrf bit should be set. for the slave mode, when clock pulses are received on scka, data in the txrx buf fer will be shifted out or data on sdia will be shifted in. to disable the spia bus scka, sdia, sdoa, scsa will become i/o pins or the other functions.
rev. 1.10 146 ?? ne 10 ? ? 01 ? rev. 1.10 147 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi spia operation all communication is carried out using the 4-line interface for either master or slave mode. the sacsen bit in the spiac1 register controls the overall function of the spia interface. setting this bit high will enable the spia interface by allowing the scsa line to be active, which can then be used to control the spia interface. if the sacsen bit is low, the spia interface will be disabled and the scsa line will be an i/o pin or the other functions and can therefore not be used for control of the spia interface. if the sacsen bit and the spiaen bit in the spiac0 register are set high, this will place the sdia line in a foating condition and the sdoa line high. if in master mode the scka line will be either high or low depending upon the clock polarity selection bit sackpolb in the spiac1 register. if in slave mode the scka line will be in a foating condition. if spiaen is low then the bus w ill be dis abled and scsa , sdia, sdoa and s cka w ill all become i/o pins or the other functions. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the spiad register. in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode: master mode ? step 1 select the clock source and master mode using the saspi2~saspi0 bits in the spiac0 control register ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb frst, this must be same as the slave device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buf fer. then use the scka and scsa lines to output the data. after this go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4.
rev. 1.10 146 ??ne 10? ?01? rev. 1.10 147 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi slave mode ? step 1 select the spi slave mode using the saspi2~saspi0 bits in the spiac0 control register ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb frst, this setting must be the same with the master device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buf fer. then wait for the master clock scka and scsa signal. after this, go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4. error detection the sawcol bit in the spiac register is provided to indicate errors during data transfer. the bit is set by the spia serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the spiad register takes place during a data transfer operation and will prevent the write operation from continuing. the overall function of the sawcol bit can be disabled or enabled by the sa_wcol bit in the sbsc register.
rev. 1.10 148 ?? ne 10 ? ? 01 ? rev. 1.10 149 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register. the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originate from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/off control, setting pcken bit to "1" enables the peripheral clock, setting pcken bit to "0" disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock output. simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f l 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bi t is high the sim int erface is enabled. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be frst initialised by the application program. bit 0 "": unimplemented, read as "0"
rev. 1.10 148 ??ne 10? ?01? rev. 1.10 149 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi interrupts interrupts are an important part of any microcontroller sys tem. when an external event or an internal function such as a timer module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0 and int1 pins, while the internal interrupts are generated by various internal functions such as the tms, lvd, sim, spia and usb. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~int c2 regi sters whic h set up the prim ary int errupts, the sec ond is the mfi0~mfi1 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disabl e individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/disable bit or "f" for request fag. function enable bit request flag notes global emi intn pin intne intnf n=0 or 1 m ? lti-f ? nction mfne mfnf n=0~ ? sim sime simf spia spiae spiaf lvd lve lvf tm tnpe tnpf n=0~ ? tnae tnaf usb usbe usbf interrupt register bit naming conventions interrupt register contents name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 usbf int1f int0f usbe int1e int0e emi intc1 mf1f mf0f lvf mf1e mf0e lve intc ? spiaf simf mf ? f mf ? f spiae sime mf ? e mf ? e mfi0 t1af t1pf t0af t0pf t1ae t1pe t0ae t0pe mfi1 t ? af t ? pf t ? af t ? pf t ? ae t ? pe t ? ae t ? pe
rev. 1.10 150 ?? ne 10 ? ? 01 ? rev. 1.10 151 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? integ register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 "": unimplemented, read as "0" bit 3~2 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges ? intc0 register bit 7 6 5 4 3 2 1 0 name usbf int1f int0f usbe int1e int0e emi r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 "": unimplemented, read as "0" bit 6 usbf : usb interrupt request flag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 usbe : usb interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.10 150 ??ne 10? ?01? rev. 1.10 151 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? intc1 register bit 7 6 5 4 3 2 1 0 name mf1f mf0f lvf mf1e mf0e lve r/w r/w r/w r r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 6 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 5 "": unimplemented, read as "0" bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3 mf1e : multi-function interrupt 1 interrupt control 0: disable 1: enable bit 2 mf0e : multi-function interrupt 0 interrupt control 0: disable 1: enable bit 1 "": unimplemented, read as "0" bit 0 lve : lvd interrupt control 0: disable 1: enable ? intc2 register bit 7 6 5 4 3 2 1 0 name spiaf simf mf ? f mf ? f spiae sime mf ? e mf ? e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 spiaf : spia interrupt request fag 0: no request 1: interrupt request bit 6 simf : sim interrupt request fag 0: no request 1: interrupt request bit 5 mf3f : multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 4 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 3 spiae : spia interrupt control 0: disable 1: enable bit 2 sime : sim interrupt control 0: disable 1: enable
rev. 1.10 15 ? ?? ne 10 ? ? 01 ? rev. 1.10 15? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 1 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 0 mf2e : multi-function interrupt 2 control 0: disable 1: enable ? mfi0 register bit 7 6 5 4 3 2 1 0 name t1af t1pf t0af t0pf t1ae t1pe t0ae t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 2 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable ? mfi1 register bit 7 6 5 4 3 2 1 0 name t ? af t ? pf t ? af t ? pf t ? ae t ? pe t ? ae t ? pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t3af : tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t3pf : tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request
rev. 1.10 15? ??ne 10? ?01? rev. 1.10 15 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 4 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t3ae : tm3 comparator a match interrupt control 0: disable 1: enable bit 2 t3pe : tm3 comparator p match interrupt control 0: disable 1: enable bit 1 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur, such as a tm compare p, compare a or compare b match etc, the relevant interrupt request flag will be set. whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit . if the ena ble bit is set high the n the program wil l jum p to it s rel evant vec tor; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a "jmp" which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti" , which retrieves the original program counter address from the stack and al lows th e mi crocontroller to co ntinue wit h no rmal ex ecution at th e po int whe re th e interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if othe r int errupt reque sts occ ur during thi s int erval, al though the int errupt wil l not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of th e in terrupt re quest fags whe n set wil l wak e-up the de vice if it is in sle ep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.10 154 ?? ne 10 ? ? 01 ? rev. 1.10 155 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi t1 af tm 1 a t1 ae t1 pf tm 1 p t1 pe 04h 08h vector t0 af tm 0 a t0 ae t0 pf tm 0 p t0 pe em i in t0 f in t0 pi n in t0 e em i int1f int1 pin int1e 10h em i mf0f m. funct.0 mf0e 14h em i mf1f m.funct.1 mf1e 18h em i mf2f m.funct.2 mf2e 1ch em i mf3f m.funct.3 mf3e 20h em i simf sim sime 24h em i spiaf spia spiae 28h em i lvf lvd lve 0ch em i usbf usb usbe xxf legend xxf xxe t3 af tm 3 a t3 ae t3 pf tm 3 p t3 pe t2 af tm 2 a t2 ae t2 pf tm 2 p t2 pe interrupt name request flags interrupt contained with in multi-function interrupts enable bits interrupt name request flags enable bits priority high low emi auto disabled in isr master enable request flag - no auto reset in isr request flag - auto reset in isr enable bit external interrupt the external interrupts are controlled by signal transitions on the pins int0 and int1. an external interrupt request will take place when the external interrupt request fags, int0f , int1f , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e, int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, int0f, int1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function.
rev. 1.10 154 ??ne 10? ?01? rev. 1.10 155 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi usb interrupt a usb interrupt request will take place when the usb interrupt request flags, usbf, is set, a situation that will occur when an endpoint is accessed. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and usb interrupt enable bit, usbe, must frst be set . whe n the int errupt is ena bled, the sta ck is not ful l and an end point is accessed, a subroutine call to the usb interrupt vector, will take place. when the interrupt is serviced, the usb interrupt request fag, usbf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. serial interface module interrupts C sim interrupt the serial interface module interrupt, known as the sim interrupt, will take place when the sim interrupt requ est fla g, simf, is set , whic h occ urs when a byt e of dat a has bee n rec eived or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must frst be set . wh en th e in terrupt is en abled, th e sta ck is not ful l an d a byt e of da ta ha s be en transmitted or received by the sim interface, a subroutine call to the respective interrupt vector, will take place. when the serial interface interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts and the simf fag will be automatically cleared as well. serial peripheral interface interrupt C spia interrupt the serial peripheral interface interrupt, also known as the spia interrupt, will take place when the spia interrupt request fag, sp iaf, is set, which occurs when a byte of data has been received or transmitted by the spia interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, spiae, must frst be set . wh en th e in terrupt is en abled, th e sta ck is not ful l an d a byt e of da ta ha s be en transmitted or rece ived by the spia int erface, a subrouti ne ca ll to the respe ctive inte rrupt vec tor, will take place. when the interrupt is serviced, the serial interface interrupt fag, spiaf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. lvd interrupt the low voltage detector interrupt, known as the lvd interrupt, will take place when the lvd interrupt request fag, lvf , is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt en able bi t, emi an d lo w vo ltage int errupt en able bi t, lve , must frst be set . when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the lvd int errupt vec tor, wil l ta ke pla ce. whe n the low vol tage int errupt is ser viced, the emi bit wil l be aut omatically cl eared to disa ble othe r int errupts and the lvf fla g wil l be automatically cleared as well. multi-function interrupt within this device there is various m ulti-function interrupts . u nlike the other independent interrupts , these interrupts have no indepe ndent source, but rathe r are formed from other existi ng int errupt sources, namely the tm interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf3f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of
rev. 1.10 156 ?? ne 10 ? ? 01 ? rev. 1.10 157 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that , alt hough the mult i-function interrupt fags wil l be aut omatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts, interrupt will not be automatically reset and must be manually reset by the application program. tm interrupts the compact and standard type tms have two interrupts each. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and standard type tms there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the interrupt functions has the capabi lity of waking up the microc ontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on th e ex ternal in terrupt pi ns, a lo w po wer sup ply vo ltage or co mparator in put ch ange may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling th e rel evant int errupt ena ble bit s, a reque sted int errupt ca n be preve nted from bei ng serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request fags , mf 0f~mf3f, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine.
rev. 1.10 156 ??ne 10? ?01? rev. 1.10 157 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their cont ents should be save d to the me mory at the begi nning of the int errupt servi ce routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low v oltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vl vd0, are used to select one of eight fxed voltages below which a low voltage con dition wil l be det ermined. a low vol tage con dition is ind icated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r r r/w r r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 6 "": unimplemented, read as "0" bit 5 lvdo : lvd output flag 0: no low voltage detect 1: low voltage detect bit 4 lvden : low voltage detector control 0: disable 1: enable bit 3 "": unimplemented, read as "0"
rev. 1.10 158 ?? ne 10 ? ? 01 ? rev. 1.10 159 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 2~0 vlvd2~vlvd0 : select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.0v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the vdd voltage may rise and fall rather slowly, at the voltage nears that of vlvd, there may be multiple bit l vdo transitions . the low voltage detector also has its own interrupt, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. th is wil l ca use th e de vice to wak e-up fr om th e sle ep or idl e mod e, ho wever if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. usb interface the usb interface is a 4-wire serial bus that allows communication between a host device and up to 127 max peripheral devices on the same bus. a token based protocol method is used by the host device for communication control. other advantages of the usb bus include live plugging and unplugging and dynamic device confguration. as the complexity of usb data protocol does not permit comprehensive usb operation information to be provided in this datasheet, the reader should therefore consult other external information for a detailed usb understanding. the device includes a usb interface function allowing for the convenient design of usb peripheral products. the usb disable/enable control bit "usbdis" is in the sysc register. if the usb is disabled, then v33o will be foa ting, th e udp/udn li nes wil l be come i/ o fu nctions, an d th e usb sie wil l be disabled.
rev. 1.10 158 ??ne 10? ?01? rev. 1.10 159 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi power plane there are three power planes for HT68FB540/ ht68fb550/ht68fb560: usb sie vdd, vddio and the mcu vdd. for the usb sie vdd will supply all circuits related to usb sie and be sourced from pin "ubus". once the usb is removed from the usb and there is no power in the usb bus, the usb sie circuit is no longer operational. for the pa and pd ports, it can be confgured using the paps1, paps0 and pdps registers to defne the pins pa0~pa7, pd4~pd7 are supplied by the mcu vdd, the v33o or the power pin vddio. for the mcu vdd, it supplies all the HT68FB540/ht68fb550/ht68fb560 circuits except the usb sie which is supply by ubus. the pe1 is pin shared with ubus pin and its "input" only. usb suspend wake-up remote wake-up if there is no signal on the usb bus for over 3ms, the devices will go into a suspend mode. the suspend flag, susp, in the usc register, will then be set high and an usb interrupt will be generated to in dicate th at th e de vices sho uld ju mp to th e susp end sta te to me et th e re quirements of the usb suspend current spec. in order to meet the requirements of the suspend current, the frmware should disable the usb clock by clearing the us bcken bit to "0 " . the suspend current can be further decreased by setting the susp2 bit in the ucc register. when the resume signal is sent out by the host, the device will be woken up the by the usb interrupt and the resume bit in the usc register will be set. to ensure correct device operation, the program must set the usbcken bit in the ucc register high and clear the susp2 bit in the ucc register. the resume signal will be cleared before the idle signal is sent out by the host and the suspend line in the usc register will change to zero. so when the mcu detects the suspend bit in the usc register, the condition of the resume line should be noted and taken into consideration. suspen d usb resume signal usb_in t the device has a remote wake up function which can wake-up the usb host by sending a wake-up pulse through rmwk in the usc register. once the usb host receives a wake-up signal from the device it will send a resume signal to the device. suspen d usb re sume signal usb_in t rmwk mi n.2.5m s min. 1 usb cl k
rev. 1.10 160 ?? ne 10 ? ? 01 ? rev. 1.10 161 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi usb interface operation the HT68FB540, ht68fb550 and ht68fb560 have 4 endpoints (ep0~ep3), 6 endpoints (ep0~ep5), an d 8 end points (e p0~ep7) re spectively. th e ep0 sup ports co ntrol tr ansfer. all ep1~ep7 support interrupt or bulk transfer. all endpoints ex cept ep0 ca n be co nfigure as 8, 16 , 32 , 64 fifo siz e by th e re gister ufc0 an d ufc1. ep0 has 8-byte fifo size. the total fifo size is 256 +8 bytes for the HT68FB540, 512 +8 bytes for the ht68fb550 and 768 +8 bytes for the ht68fb560. as the usb fifo is assigned from the last bank of the data ram and has a start address of 0ffh to the upper address, dependent on the fifo size, if the corresponding data ram bank is used for both general purpose ram and the usb fifo, special care should be taken that the ram equ defnition should not overlap with the usb fifo ram address. the urd in the usc register is the usb reset signal control function defnition bit. the usb fifo size definition for in/out control depends on the ufc, ufien and ufoen registers. if out 1 not used, then the out 1 fifo will not be defned and in 2 will be defned as in 1 afterwards. n 80 h nbfh "n"= bank 1~0 ? last bank first defined general p?rpose data memory out ? ( 8 bytes ) in ? ( 8 bytes ) out ? ( 16 bytes ) in ? ( 16 bytes ) out 1 ( 8 bytes ) in 1 ( 8 bytes ) nc 0h nc 7h nc 8h ncfh nd 0h ndfh ne 0h nefh nf 0h nf 7h nf 8h nffh ht 68fb 540 usb fifo size defne
rev. 1.10 160 ??ne 10? ?01? rev. 1.10 161 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi usb interface registers the usb interface has a series of registers associated with its operation. sysc register bit 7 6 5 4 3 2 1 0 name clk_ad ? usbdis rubus hfv r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 clk_adj : pll clock automatic adjustment function: pll related control bit, described elsewhere bit 6 usbdis : usb sie control bit 0: enable 1: disable bit 5 rubus : ubus pin pull low resistor 0: enable 1: disable bit 4~3 "": unimpleme nted, read as "0" bit 2 hfv : non-usb mode high frequency voltage control 0: for usb mode - bit must be cleared to zero. 1: for non-usb mode - bit must be set high. ensures that the higher frequency can work at lower voltages. a higher frequency is >8mhz and is used for the system clock f h . bit 1~0 "": unimpleme nted, read as "0" usb_stat register bit 7 6 5 4 3 2 1 0 name ps ? _cko ps ? _dao ps ? _cki ps ? _dai se1 se0 pu esd r/w w w r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ps2_cko : output for driving udp/gpio0 pin, when work under 3d ps2 mouse function. default value is "1". bit 6 ps2_dao : output for driving udn/gpio1 pin, when work under 3d ps2 mouse function. default value is "1". bit 5 ps2_cki : udp/gpio0 input. bit 4 ps2_dai : udn/gpio1 input. bit 3 se1 : this bit is used to indicate the sie has detected a se1 noise in the usb bus. this bit is set by sie and clear by f/w. bit 2 se0 : this bit is used to indicate the sie has detected a se0 noise in the usb bus. this bit is set by sie and clear by f/w. bit 1 pu : bit1=1, udp, and udn have a 600k pull-high bit1=0, no pull-high (default on mcu reset) bit 0 esd : this bit will set to "1" when there is esd issue. this bit is set by sie and cleared by f/w.
rev. 1.10 16 ? ?? ne 10 ? ? 01 ? rev. 1.10 16? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi uint register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name ep ? en ep ? en ep1en ep0en r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 : "": unimplemented, read as "0" bit 3 ep3en : usb endpoint3 interrupt control bit. 0: disable 1: enable bit 2 ep2en : usb endpoint2 interrupt control bit. 0: disable 1: enable bit 1 ep1en : usb endpoint1 interrupt control bit. 0: disable 1: enable bit 0 ep0en : usb endpoint0 interrupt control bit. 0: disable 1: enable ? ht68fb550 bit 7 6 5 4 3 2 1 0 name ep5en ep4en ep ? en ep ? en ep1en ep0en r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 6 : "": unimplemented, read as "0" bit 5 ep5en : usb endpoint5 interrupt control bit. 0: disable 1: enable bit 4 ep4en : usb endpoint4 interrupt control bit. 0: disable 1: enable bit 3 ep3en : usb endpoint3 interrupt control bit. 0: disable 1: enable bit 2 ep2en : usb endpoint2 interrupt control bit. 0: disable 1: enable bit 1 ep1en : usb endpoint1 interrupt control bit. 0: disable 1: enable bit 0 ep0en : usb endpoint0 interrupt control bit. 0: disable 1: enable
rev. 1.10 16? ??ne 10? ?01? rev. 1.10 16 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb560 bit 7 6 5 4 3 2 1 0 name ep7en ep6en ep5en ep4en ep ? en ep ? en ep1en ep0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ep7en : usb endpoint7 interrupt control bit. 0: disable 1: enable bit 6 ep6en : usb endpoint6 interrupt control bit. 0: disable 1: enable bit 5 ep5en : usb endpoint5 interrupt control bit. 0: disable 1: enable bit 4 ep4en : usb endpoint4 interrupt control bit. 0: disable 1: enable bit 3 ep3en : usb endpoint3 interrupt control bit. 0: disable 1: enable bit 2 ep2en : usb endpoint2 interrupt control bit. 0: disable 1: enable bit 1 ep1en : usb endpoint1 interrupt control bit. 0: disable 1: enable bit 0 ep0en : usb endpoint0 interrupt control bit. 0: disable 1: enable usc register bit 7 6 5 4 3 2 1 0 name urd selps ? pll selusb resume urst rmwk susp r/w r/w r/w r/w r/w r r/w r/w r por 1 0 0 0 0 0 0 0 bit 7 urd : usb reset signal control function defnition 0: usb reset signal cannot mcu 1: usb reset signal will reset mcu bit 6 selps2 : ps2 mode select bit 0: not ps2 mode 1: ps2 mode when the selps2 bit is set high, the ps2 function is selected and the pin-shared pins, udn/gpio0 and udp/ gpio1, will become the gpio0 and gpio1 general purpose i/o functions which can be used to be the data and clk pins for the ps2. bit 5 pll : pll control bit 0: turn-on pll 1: turn-off pll
rev. 1.10 164 ?? ne 10 ? ? 01 ? rev. 1.10 165 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 4 selusb : usb mode and v33o on/of f select bit 0: not usb mode, turn-off v33o 1: usb mode, turn-on v33o when the selusb bit is set high, the usb and v33o functions is selected and the pin-shared pins, udn/gpio0 and udp/gpio1, will become the udn and udp pins for the usb. selusb selps2 usb and ps2 mode description 0 0 1.no mode s ? pported 2.v33o pin not output and it will foating ? .udn/gpio0 and udp/gpio1 pins cannt o ? tp ? t 0 1 1.ps ? mode ? .v ?? o pin o ? tp ? t vdd ? .udn/gpio0 and udp/gpio1 pins will become the gpio0 and gpio1 pins, which can output by frmware 1 x 1.usb mode 2.v33o output 3.3v 3.udn/gpio0 and udp/gpio1 pins will become the udn and udp pins x: dont care bit 3 resume : usb resume indication bit 0: susp bit goes to "0" 1: leave the suspend mode when the usb leaves the suspend mode, this bit is set to "1" (set by sie). when the resume is set by sie, an interrupt will be generated to wake-up the mcu. in order to detect the suspend state, the mcu should set usbcken and clear susp2 (in the ucc register) to enable the sie detect function. resum e will be cleared when the susp goes to "0". when the mcu is detecting the susp, the condition of resume (causes the mcu to wake-up) should be noted and taken into consideration. bit 2 urst : usb reset indication bit 0: no usb reset 1: usb reset occurred this bit is set/cleared by the usb sie. this bit is used to detect a usb reset event on the usb bus. when this bit is set to "1", this indicates that a usb reset has occurred and that a usb interrupt will be initialized. bit 1 rmwk : usb remote wake-up command 0: no remote wake-up 1: remote wake-up it is set by mcu to le ave th e usb host le aving th e suspe nd mo de. th is bit is set to produce a high pulse width of 4 m s to indicate that the usb host has left the suspend mode. bit 0 susp : usb suspend indication 0: not in the suspend mode 1: enter the suspend mode when this bit is set to 1 (set by sie), it indicates that the usb bus has entered the suspend mode. the usb interrupt is also triggered when this bit changes from low to high.
rev. 1.10 164 ??ne 10? ?01? rev. 1.10 165 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi usr register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name ep ? f ep ? f ep1f ep0f r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 : "": unimplemented, read as "0" bit 3 ep3f : endpoint 3 accessed detection 0: not accessed 1: accessed bit 2 ep2f : endpoint 2 accessed detection 0: not accessed 1: accessed bit 1 ep1f : endpoint 1 accessed detection 0: not accessed 1: accessed bit 0 ep0f : endpoint 0 accessed detection 0: not accessed 1: accessed ? ht68fb550 bit 7 6 5 4 3 2 1 0 name ep5f ep4f ep ? f ep ? f ep1f ep0f r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : "": unimplemented, read as "0" bit 5 ep5f : endpoint 5 accessed detection 0: not accessed 1: accessed bit 4 ep4f : endpoint 4 accessed detection 0: not accessed 1: accessed bit 3 ep3f : endpoint 3 accessed detection 0: not accessed 1: accessed bit 2 ep2f : endpoint 2 accessed detection 0: not accessed 1: accessed bit 1 ep1f : endpoint 1 accessed detection 0: not accessed 1: accessed bit 0 ep0f : endpoint 0 accessed detection 0: not accessed 1: accessed
rev. 1.10 166 ?? ne 10 ? ? 01 ? rev. 1.10 167 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb560 bit 7 6 5 4 3 2 1 0 name ep7f ep6f ep5f ep4f ep ? f ep ? f ep1f ep0f r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ep7f : endpoint 7 accessed detection 0: not accessed 1: accessed bit 6 ep6f : endpoint 6 accessed detection 0: not accessed 1: accessed bit 5 ep5f : endpoint 5 accessed detection 0: not accessed 1: accessed bit 4 ep4f : endpoint 4 accessed detection 0: not accessed 1: accessed bit 3 ep3f : endpoint 3 accessed detection 0: not accessed 1: accessed bit 2 ep2f : endpoint 2 accessed detection 0: not accessed 1: accessed bit 1 ep1f : endpoint 1 accessed detection 0: not accessed 1: accessed bit 0 ep0f : endpoint 0 accessed detection 0: not accessed 1: accessed ucc register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name rctrl sysclk fsys16mhz susp ? usbcken eps1 eps0 r/w r/w r/w r/w r/w r/w r r/w r/w por 0 0 0 0 0 0 0 0 bit 7 rctrl : 7.5k resistor between udp and ubus control bit 0: no 7.5k resistor between udp and ubus 1: has 7.5k resistor between udp and ubus bit 6 sysclk : specify mcu oscillator frequency indication bit 0: 12mhz crystal oscillator or resonator, clear this bit to "0". 1: 6mhz crystal oscillator or resonator, set this bit to "1". bit 5 fsys16mhz : mcu system clock source control bit 0: from osc. 1: from pll output 16mhz. bit 4 susp2 : reduce power consumption in suspend mode control bit 0: in normal mode 1: in halt mode, set this bit to "1" for reducing power consumption bit 3 usbcken : usb clock control bit 0: disable 1: enable bit 2 "": unimplemented, read as "0" bit 1~0 eps1, eps0 : accessing endpoint fifo selection 00: select endpoint 0 fifo (control) 01: select endpoint 1 fifo 10: select endpoint 2 fifo 11: select endpoint 3 fifo
rev. 1.10 166 ??ne 10? ?01? rev. 1.10 167 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb550 bit 7 6 5 4 3 2 1 0 name rctrl sysclk fsys16mhz susp ? usbcken eps ? eps1 eps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 rctrl : 7.5k resistor between udp and ubus control bit 0: no 7.5k resistor between udp and ubus 1: has 7.5k resistor between udp and ubus bit 6 sysclk : specify mcu oscillator frequency indication bit 0: 12mhz crystal oscillator or resonator, clear this bit to "0". 1: 6mhz crystal oscillator or resonator, set this bit to "1". bit 5 fsys16mhz : mcu system clock source control bit 0: from osc. 1: from pll output 16mhz. bit 4 susp2 : reduce power consumption in suspend mode control bit 0: in normal mode 1: in halt mode, set this bit to "1" for reducing power consumption bit 3 usbcken : usb clock control bit 0: disable 1: enable bit 2~0 eps2, eps1, eps0 : accessing endpoint fifo selection 000: select endpoint 0 fifo (control) 001: select endpoint 1 fifo 010: select endpoint 2 fifo 011: select endpoint 3 fifo 100: select endpoint 4 fifo 101~111: select endpoint 5 fifo ? ht68fb560 bit 7 6 5 4 3 2 1 0 name rctrl sysclk fsys16mhz susp ? usbcken eps ? eps1 eps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 rctrl : 7.5k resistor between udp and ubus control bit 0: no 7.5k resistor between udp and ubus 1: has 7.5k resistor between udp and ubus bit 6 sysclk : specify mcu oscillator frequency indication bit 0: 12mhz crystal oscillator or resonator, clear this bit to "0". 1: 6mhz crystal oscillator or resonator, set this bit to "1". bit 5 fsys16mhz : mcu system clock source control bit 0: from osc. 1: from pll output 16mhz. bit 4 susp2 : reduce power consumption in suspend mode control bit 0: in normal mode 1: in halt mode, set this bit to "1" for reducing power consumption bit 3 usbcken : usb clock control bit 0: disable 1: enable bit 2~0 eps2, eps1, eps0 : accessing endpoint fifo selection 000: select endpoint 0 fifo (control) 001: select endpoint 1 fifo 010: select endpoint 2 fifo 011: select endpoint 3 fifo 100: select endpoint 4 fifo 101: select endpoint 5 fifo 110: select endpoint 6 fifo 111: select endpoint 7 fifo
rev. 1.10 168 ?? ne 10 ? ? 01 ? rev. 1.10 169 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi awr register bit 7 6 5 4 3 2 1 0 name ad6 ad5 ad4 ad ? ad ? ad1 ad0 wken r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~1 ad6~ad0 : usb device address bit 0 wken : usb remote-wake-up control bit 0: disable 1: enable the awr register contains the current address and a remote wake up function control bit. the initial value of awr is "00h". the address value extracted from the usb command has not to be loaded into this register until the setup stage has fnished. stlo register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name stlo ? stlo ? stlo1 stlo0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 "": unimplemented, read as "0" bit 3~0 stlo3~stlo0 : fifo out stall endpoints indication bits 0: not stall 1: stall the stlo regi ster shows if the corre sponding endpoint has worked properl y or not. as soon as endpoint improper operation occurs, the related bit in the stlo register has to be set high. the stlo register bits will be cleared by a usb reset signal and a setup token event. ? ht68fb550 bit 7 6 5 4 3 2 1 0 name stlo5 stlo4 stlo ? stlo ? stlo1 stlo0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 "": unimplemented, read as "0" bit 5~0 stlo5~stlo0 : fifo out stall endpoints indication bits 0: not stall 1: stall the stlo regi ster shows if the corre sponding endpoint has worked properl y or not. as soon as endpoint improper operation occurs, the related bit in the stlo register has to be set high. the stlo register bits will be cleared by a usb reset signal and a setup token event.
rev. 1.10 168 ??ne 10? ?01? rev. 1.10 169 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb560 bit 7 6 5 4 3 2 1 0 name stlo7 stlo6 stlo5 stlo4 stlo ? stlo ? stlo1 stlo0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stlo7~stlo0 : fifo out stall endpoints indication bits 0: not stall 1: stall the stlo regi ster shows if the corre sponding endpoint has worked properl y or not. as soon as endpoint improper operation occurs, the related bit in the stlo register has to be set high. the stlo register bits will be cleared by a usb reset signal and a setup token event. stli register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name stli ? stli ? stli1 stli0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 : "": unimplemented, read as "0" bit 3~0 stli3~stli0 : fifo in stall endpoints indication bits 0: not stall 1: stall the stli register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper operation occurs, the related bit in the stli register has to be set high. the stli register bits will be cleared by a usb reset signal and a setup token event. ? ht68fb550 bit 7 6 5 4 3 2 1 0 name stli5 stli4 stli ? stli ? stli1 stli0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 : "": unimplemented, read as "0" bit 5~0 stli5~stli0 : fifo in stall endpoints indication bits 0: not stall 1: stall the stli register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper operation occurs, the related bit in the stli register has to be set high. the stli register bits will be cleared by a usb reset signal and a setup token event.
rev. 1.10 170 ?? ne 10 ? ? 01 ? rev. 1.10 171 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb560 bit 7 6 5 4 3 2 1 0 name stli7 stli6 stli5 stli4 stli ? stli ? stli1 stli0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stli7 ~ stli0 : fifo in stall endpoints indication bits 0: not stall 1: stall the stli register shows if the corresponding endpoint has worked properly or not. as soon as endpoint improper operation occurs, the related bit in the stli register has to be set high. the stli register bits will be cleared by a usb reset signal and a setup token event. sies register bit 7 6 5 4 3 2 1 0 name nmi crcf nak in out err aset r/w r/w r/w r r r r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 nmi : nak token interrupt mask fag 0: interrupt enable 1: interrupt disable if this bit set, when the device sent a nak token to the host, an interrupt will be disabled. otherwise if this bit is cleared, when the device sends a nak token to the host, it will enter the interrupt sub-routine. this bit is used for all endpoint. bit 6 crcf : crc error detection fag 0: no error 1: error this bit will be set to "1" when there are the following three conditions happened: crc error, pid error, bit stuffng error. this bit is set by sie and cleared by f/w . bit 5 "": unimplemented, read as "0" bit 4 nak : ack error detection fag 0: no error 1: error this bit will set to "1" once sie discover there are some error condition so the sie is not response (nak or ack or dat a) for the usb token. this bit is set by sie and cleared by f/w. bit 3 in : current usb receiving signal indicator 0: low 1: high this bit is used to indicate the current usb receiving signal from pc host is in token. bit 2 out : usb out token indicator 0: low 1: high this bit is use d to in dicate th e out to ken (e xcept th e out ze ro le ngth to ken) ha s been received. the frmware clears this bit after the out data has been read. also, this bit will be cleared by sie after the next valid setup token is received.
rev. 1.10 170 ??ne 10? ?01? rev. 1.10 171 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 1 err : fifo accessed error indicator 0: no error 1: error this bit is used to indicate that some errors have occurred when the fifo is accessed. this bit is set by sie and should be cleared by firmware. this bit is used for all endpoint. bit 0 aset : device address updated method control bit 0: update address after an written address to the awr register 1: update address after pc host read out data this bit is used to confgure the sie to automatically change the device address by the value stored in the awr register. when this bit is set to "1" by frmware, the sie will update the device address by the value stored in the awr register after the pc host has successfully read the data from he device by an in operation. otherwise, when this bit is cleared to"0", the sie will update the device address immediately after an address is written to the awr register. so, in order to work properly, the frmware has to clear this bit after a next valid setup token is received. misc register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name len0 ready setcmd e ? idf clear tx request r/w r r r/w r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 len0 : 0-sized packet indication fag 0: not 0-sized packet 1: 0-sized packet this bit is used to show that the host sent a 0-sized packet to the mcu. this bit must be cleared by a read action to the corresponding fifo. bit 6 ready : desired fifo ready indication fag 0: not ready 1: ready bit 5 setcmd : setup command indication fag 0: not setup command 1: setup command this bit is used to show that the data in the fif o is a s etup command. this bit is set by hardware and cleared by firmware. bit 4 "": unimplemented, read as "0" bit 3 e3idf : endpoint 3 input fifo selection 0: single buffer 1: double buffer bit 2 clear : clear fifo function control bit 0: disable 1: enable mcu requests to cl ear the fifo, eve n if the fifo is not rea dy. afte r cl earing the fifo, the usb interface will send force_tx_err to tell the host that data under-run if the host wants to read data.
rev. 1.10 17 ? ?? ne 10 ? ? 01 ? rev. 1.10 17? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 1 tx : data writing to fifo status indication fag 0: data writing fnished 1: data writing to fifo to represent the dire ction and tra nsition end mcu ac cess. whe n set to logi c 1, the mcu desires to write data to the fifo. after fnishing, this bit must be set to logic 0 before t erminating r equest t o r epresent t ransition e nd. for an mcu r ead o peration, thi s bit must be set to logic 0 and set to logic 1 after fnishing. bit 0 request : desired fifo request status indication fag 0: no request 1: request after setting the status of the desired one, fifo can be requested by setting this bit high.after fnishing, this bit must be set low. ? ht68fb550/ht68fb560 bit 7 6 5 4 3 2 1 0 name len0 ready setcmd e4odf e ? idf clear tx request r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 len0 : 0-sized packet indication fag 0: not 0-sized packet 1: 0-sized packet this bit is used to show that the host sent a 0-sized packet to the mcu. this bit must be cleared by a read action to the corresponding fifo. bit 6 ready : desired fifo ready indication fag 0: not ready 1: ready bit 5 setcmd : setup command indication fag 0: not setup command 1: setup command this bit is used to show that the data in the fif o is a s etup command. this bit is set by hardware and cleared by firmware. bit 4 e4odf : endpoint 4 output fifo selection 0: single buffer 1: double buffer bit 3 e3idf : endpoint 3 input fifo selection 0: single buffer 1: double buffer bit 2 clear : clear fifo function control bit 0: disable 1: enable mcu requests to cl ear the fifo, eve n if the fifo is not rea dy. afte r cl earing the fifo, the usb interface will send force_tx_err to tell the host that data under-run if the host wants to read data. bit 1 tx : data writing to fifo status indication fag 0: data writing fnished 1: data writing to fifo to represent the dire ction and tra nsition end mcu ac cess. whe n set to logi c 1, the mcu desires to write data to the fifo. after fnishing, this bit must be set to logic 0 before t erminating r equest t o r epresent t ransition end . fo r a n mcu r ead o peration, thi s bit must be set to logic 0 and set to logic 1 after fnishing. bit 0 request : desired fifo request status indication fag 0: no request 1: request after setting the status of the desired one, fifo can be requested by setting this bit high.after fnishing, this bit must be set low.
rev. 1.10 17? ??ne 10? ?01? rev. 1.10 17 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ufoen register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name seto ? seto ? seto1 datatg r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 "": unimplemented, read as "0" bit 3 seto3 : ep3 output fifo control bit 0: disable 1: enable bit 2 seto2 : ep2 output fifo control bit 0: disable 1: enable bit 1 seto1 : ep1 output fifo control bit 0: disable 1: enable bit 0 datatg : data token toggle bit 0: low 1: high ? ht68fb550 bit 7 6 5 4 3 2 1 0 name seto5 seto4 seto ? seto ? seto1 datatg r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 6 "": unimplemented, read as "0" bit 5 seto5 : ep5 output fifo control bit 0: disable 1: enable bit 4 seto4 : ep4 output fifo control bit 0: disable 1: enable bit 3 seto3 : ep3 output fifo control bit 0: disable 1: enable bit 2 seto2 : ep2 output fifo control bit 0: disable 1: enable bit 1 seto1 : ep1 output fifo control bit 0: disable 1: enable bit 0 datatg : data token toggle bit 0: low 1: high
rev. 1.10 174 ?? ne 10 ? ? 01 ? rev. 1.10 175 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb560 bit 7 6 5 4 3 2 1 0 name seto7 seto6 seto5 seto4 seto ? seto ? seto1 datatg r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 seto7 : ep7 output fifo control bit 0: disable 1: enable bit 6 seto6 : ep6 output fifo control bit 0: disable 1: enable bit 5 seto5 : ep5 output fifo control bit 0: disable 1: enable bit 4 seto4 : ep4 output fifo control bit 0: disable 1: enable bit 3 seto3 : ep3 output fifo control bit 0: disable 1: enable bit 2 seto2 : ep2 output fifo control bit 0: disable 1: enable bit 1 seto1 : ep1 output fifo control bit 0: disable 1: enable bit 0 datatg : data token toggle bit 0: low 1: high ufien register ? HT68FB540 bit 7 6 5 4 3 2 1 0 name seti ? seti ? seti1 fifo_def r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 "": unimplemented, read as "0" bit 3 seti3 : ep3 input fifo control bit 0: disable 1: enable bit 2 seti2 : ep2 input fifo control bit 0: disable 1: enable bit 1 seti1 : ep1 input fifo control bit 0: disable 1: enable bit 0 fifo_def : fifo confguration redefned control bit 0: disable 1: enable if this bit is set to "1", the sie should redefne the fifo confguration. this bit will be automatically cleared by sie.
rev. 1.10 174 ??ne 10? ?01? rev. 1.10 175 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb550 bit 7 6 5 4 3 2 1 0 name seti5 seti4 seti ? seti ? seti1 fifo_def r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 "": unimplemented, read as "0" bit 5 seti5 : ep5 input fifo control bit 0: disable 1: enable bit 4 seti4 : ep4 input fifo control bit 0: disable 1: enable bit 3 seti3 : ep3 input fifo control bit 0: disable 1: enable bit 2 seti2 : ep2 input fifo control bit 0: disable 1: enable bit 1 seti1 : ep1 input fifo control bit 0: disable 1: enable bit 0 fifo_def : fifo confguration redefned control bit 0: disable 1: enable if this bit is set to "1", the sie should redefne the fifo confguration. this bit will be automatically cleared by sie. ? ht68fb560 bit 7 6 5 4 3 2 1 0 name seti7 seti6 seti5 seti4 seti ? seti ? seti1 fifo_def r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 seti7 : ep7 input fifo control bit 0: disable 1: enable bit 6 seti6 : ep6 input fifo control bit 0: disable 1: enable bit 5 seti5 : ep5 input fifo control bit 0: disable 1: enable bit 4 seti4 : ep4 input fifo control bit 0: disable 1: enable bit 3 seti3 : ep3 input fifo control bit 0: disable 1: enable bit 2 seti2 : ep2 input fifo control bit 0: disable 1: enable
rev. 1.10 176 ?? ne 10 ? ? 01 ? rev. 1.10 177 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi bit 1 seti1 : ep1 input fifo control bit 0: disable 1: enable bit 0 fifo_def : fifo confguration redefned control bit 0: disable 1: enable if this bit is set to "1", the sie should redefne the fifo confguration. this bit will be automatically cleared by sie. ufc0 register bit 7 6 5 4 3 2 1 0 name e ? fs1 e ? fs0 e ? fs1 e ? fs0 e1fs1 e1fs0 r/w r/w r/w r/w r/w r/w r/w r r por 0 0 0 0 0 0 0 0 bit 7~6 e3fs1, e3sf0 : endpoint 3 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 5~4 e2fs1, e2sf0 : endpoint 2 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 3~2 e1fs1, e1sf0 : endpoint 1 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 1~0: "": unimplemented, read as "0" ufc1 register ? ht68fb550 bit 7 6 5 4 3 2 1 0 name e5fs1 e5fs0 e4fs1 e4fs0 r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 : "": unimplemented, read as "0" bit 3~2 e5fs1, e5sf0 : endpoint 5 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 1~0 e4fs1, e4sf0 : endpoint 4 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte
rev. 1.10 176 ??ne 10? ?01? rev. 1.10 177 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb560 bit 7 6 5 4 3 2 1 0 name e7fs1 e7fs0 e6fs1 e6fs0 e5fs1 e5fs0 e4fs1 e4fs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 e7fs1, e7sf0 : endpoint 7 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 5~4 e6fs1, e6sf0 : endpoint 6 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 3~2 e5fs1, e5sf0 : endpoint 5 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte bit 1~0 e4fs1, e4sf0 : endpoint 4 fifo size selection 00: 8-byte 01: 16-byte 10: 32-byte 11: 64-byte usb endpoint accessing registers ? HT68FB540 register name bit 7 6 5 4 3 2 1 0 fifo0 d7 d6 d5 d4 d ? d ? d1 d0 fifo1 d7 d6 d5 d4 d ? d ? d1 d0 fifo ? d7 d6 d5 d4 d ? d ? d1 d0 fifo ? d7 d6 d5 d4 d ? d ? d1 d0 ? ht68fb550 register name bit 7 6 5 4 3 2 1 0 fifo0 d7 d6 d5 d4 d ? d ? d1 d0 fifo1 d7 d6 d5 d4 d ? d ? d1 d0 fifo ? d7 d6 d5 d4 d ? d ? d1 d0 fifo ? d7 d6 d5 d4 d ? d ? d1 d0 fifo4 d7 d6 d5 d4 d ? d ? d1 d0 fifo5 d7 d6 d5 d4 d ? d ? d1 d0
rev. 1.10 178 ?? ne 10 ? ? 01 ? rev. 1.10 179 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ? ht68fb560 register name bit 7 6 5 4 3 2 1 0 fifo0 d7 d6 d5 d4 d ? d ? d1 d0 fifo1 d7 d6 d5 d4 d ? d ? d1 d0 fifo ? d7 d6 d5 d4 d ? d ? d1 d0 fifo ? d7 d6 d5 d4 d ? d ? d1 d0 fifo4 d7 d6 d5 d4 d ? d ? d1 d0 fifo5 d7 d6 d5 d4 d ? d ? d1 d0 fifo6 d7 d6 d5 d4 d ? d ? d1 d0 fifo7 d7 d6 d5 d4 d ? d ? d1 d0 confguration options confguration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are select ed they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed system oscillator selection - f h: 1. hirc (defa ? lt) ? . hxt crystal mode frequency option ? clock mode freq ? ency: 1. 1 ? mhz ? . 6mhz i/o or vddio option ? i/o or vddio pin control bit: 1. vddio (defa ? lt) ? . i/o (pe0)
rev. 1.10 178 ??ne 10? ?01? rev. 1.10 179 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi application circuits vdd/ubus vss 100kw res vdd v33o udn udp sim hvdd 300w 0.1f spi / i 2 c device i/o tp0 tp1 tp2 vdd b g r 1k w 1k w 1k w 56 w 65w 120w q1 3904 q2 3904 q3 3904 vbus d- d+ vss 0.1f 0.1f 10f 47pf 47pf 33w key matrix input 0.1f 33w
rev. 1.10 180 ?? ne 10 ? ? 01 ? rev. 1.10 181 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to tha t new addre ss, one more cyc le wil l be requi red. exa mples of such inst ructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of dat a wit hin the mi crocontroller program is one of the most freque ntly used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most im portant dat a tra nsfer appl ications is to rec eive dat a from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller appl ications. wi thin the holt ek mi crocontroller inst ruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.10 180 ??ne 10? ?01? rev. 1.10 181 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holt ek mi crocontroller inst ruction set. as wit h the ca se of most inst ructions invol ving data manipulation, da ta mu st pa ss th rough th e acc umulator whi ch ma y in volve ad ditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming app lications where dat a ca n be rota ted from an int ernal regi ster int o the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is norma lly im plemented by using regi sters. however , when working wit h la rge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.10 18 ? ?? ne 10 ? ? 01 ? rev. 1.10 18? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] addm a ? [m] add a ? x adc a ? [m] adcm a ? [m] sub a ? x sub a ? [m] subm a ? [m] sbc a ? [m] sbcm a ? [m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry s ? btract immediate data from the acc s ? btract data memory from acc s ? btract data memory from acc with res ? lt in data memory s ? btract data memory from acc with carry s ? btract data memory from acc with carry ? res ? lt in data memory decimal adj ? st acc for addition with res ? lt in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov c logic operation and a ? [m] or a ? [m] xor a ? [m] andm a ? [m] orm a ? [m] xorm a ? [m] and a ? x or a ? x xor a ? x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with res ? lt in acc 1 1 1 1 note 1note 1note 1 1 1 1note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with res ? lt in acc increment data memory decrement data memory with res ? lt in acc decrement data memory 1 1 note 1 1note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with res ? lt in acc rotate data memory right rotate data memory right thro ? gh carry with res ? lt in acc rotate data memory right thro ? gh carry rotate data memory left with res ? lt in acc rotate data memory left rotate data memory left thro ? gh carry with res ? lt in acc rotate data memory left thro ? gh carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a ? [m] mov [m] ? a mov a ? x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none
rev. 1.10 18? ??ne 10? ?01? rev. 1.10 18 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi mnemonic description cycles flag affected branch ? mp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a ? x reti ?? mp ? nconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with res ? lt in acc skip if decrement data memory is zero with res ? lt in acc s ? bro ? tine call ret ? rn from s ? bro ? tine ret ? rn from s ? bro ? tine and load immediate data to acc ret ? rn from interr ? pt ? 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note ? ? ? ? none none none none none none none none none none none none none table read tabrd [m] tabrdl [m] read table (c ? rrent page) to tblh and data memory read table (last page) to tblh and data memory ? note ? note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt ? swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with res ? lt in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to ? pdf to ? pdf to ? pdf none none to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf fags may be af fected by the execution status. the to and pdf fags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.10 184 ?? ne 10 ? ? 01 ? rev. 1.10 185 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi instruction defnition adc a,[m] add da ta me mory to ac c wit h c arry description the co ntents of th e sp ecifed da ta me mory, ac cumulator an d th e ca rry fag ar e ad ded. the res ult i s st ored in th e ac cumulator. operation acc ac c + [m ] + c affected fag(s) ov, z, ac , c adcm a,[m] add ac c to da ta me mory wit h c arry description the co ntents of th e sp ecifed da ta me mory, ac cumulator an d th e ca rry fag ar e ad ded. the res ult i s st ored in th e spe cifed da ta me mory. operation [m] ac c + [m] + c affected fag(s) ov, z, ac , c add a,[m] add da ta memor y to ac c description the co ntents of th e sp ecifed da ta me mory an d th e ac cumulator ar e ad ded. the res ult i s st ored in th e ac cumulator. operation acc ac c + [m ] affected fag(s) ov, z, ac , c add a,x add immediate d ata to ac c description the co ntents of th e ac cumulator an d th e sp ecifed imm ediate da ta ar e ad ded. the res ult i s st ored in th e ac cumulator. operation acc ac c + x affected fag(s) ov, z, ac , c addm a,[m] add ac c to da ta me mory description the co ntents of th e sp ecifed da ta me mory an d th e ac cumulator ar e ad ded. the res ult i s st ored in th e spe cifed da ta me mory. operation [m] ac c + [m] affected fag(s) ov, z, ac , c and a,[m] logical an d da ta memor y to ac c description data in th e ac cumulator an d th e sp ecifed da ta me mory pe rform a bit wise lo gical an d operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c an d [m ] affected fag(s) z and a,x logical and imm ediate d ata to ac c description data in th e ac cumulator an d th e sp ecifed imm ediate da ta pe rform a bit wi se lo gical an d operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c an d x affected fag(s) z andm a,[m] logical an d ac c to da ta me mory description data in th e sp ecifed da ta me mory an d th e ac cumulator pe rform a bit wise lo gical an d operation. th e res ult i s st ored in th e da ta me mory. operation [m] ac c a nd [m] affected fag(s) z
rev. 1.10 184 ??ne 10? ?01? rev. 1.10 185 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi call addr subroutine ca ll description unconditionally cal ls a su broutine at th e sp ecifed ad dress. the pr ogram cou nter th en increments by 1 to ob tain th e ad dress of th e ne xt in struction wh ich is th en pu shed on to th e stack. th e spe cifed add ress i s th en l oaded an d th e pro gram co ntinues ex ecution fro m th is new add ress. as th is in struction req uires an add itional ope ration, i t i s a tw o cy cle in struction. operation stack pr ogram c ounter + 1 program cou nter ad dr affected fag(s) none clr [m] clear da ta memor y description each bi t of th e sp ecifed da ta me mory is clea red to 0. operation [m] 0 0h affected fag(s) none clr [m].i clear bit of da ta me mory description bit i of th e sp ecifed da ta me mory is clea red to 0. operation [m].i 0 affected fag(s) none clr wdt clear wa tchdog ti mer description the to , pd f fag s an d th e wd t ar e all cl eared. operation wdt clea red to 0 pdf 0 affected fag(s) to, pd f clr wdt1 pre-clear wa tchdog ti mer description the to , pd f fa gs an d th e wd t are al l cl eared. no te th at th is in struction wo rks in conjunction wit h cl r wd t2 an d mu st be ex ecuted alt ernately wit h cl r wd t2 to ha ve effect. re petitively ex ecuting th is in struction wit hout alt ernately ex ecuting cl r wd t2 wi ll have no ef fect. operation wdt clea red to 0 pdf 0 affected fag(s) to, pd f clr wdt2 pre-clear wa tchdog ti mer description the to , pd f fa gs a nd th e wd t a re al l c leared. no te th at thi s in struction wo rks in c onjunction with cl r wd t1 an d mu st be ex ecuted alt ernately wit h cl r wd t1 to ha ve ef fect. re petitively ex ecuting th is in struction wit hout alt ernately ex ecuting cl r wd t1 wi ll ha ve no e f fect. operation wdt clea red to 0 pdf 0 affected fag(s) to, pd f cpl [m] complement da ta memor y description each bi t o f th e sp ecifed da ta me mory is lo gically c omplemented (1 s c omplement). bi ts whi ch previously co ntained a 1 ar e ch anged to 0 an d vi ce ve rsa. operation [m] [m] affected fag(s) z
rev. 1.10 186 ?? ne 10 ? ? 01 ? rev. 1.10 187 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi cpla [m] complement da ta me mory wit h re sult in ac c description each bi t o f th e sp ecifed da ta me mory is lo gically c omplemented (1 s c omplement). bi ts whi ch previously co ntained a 1 ar e ch anged to 0 an d vi ce ve rsa. the co mplemented re sult is sto red in the ac cumulator an d th e co ntents of th e da ta me mory re main un changed. operation acc [m] affected fag(s) z daa [m] decimal-adjust ac c fo r ad dition wit h re sult in da ta me mory description convert th e co ntents of th e ac cumulator val ue to a bc d (b inary co ded de cimal) val ue resulting fro m th e pre vious add ition of tw o bc d va riables. if th e l ow ni bble i s g reater th an 9 or if ac fag is se t, th en a val ue of 6 wi ll be ad ded to th e lo w ni bble. ot herwise th e lo w ni bble remains un changed. if th e hi gh ni bble is gr eater th an 9 or if th e c fag is se t, th en a val ue of 6 will be ad ded to th e hi gh ni bble. es sentially, th e de cimal co nversion is pe rformed by ad ding 00h, 06 h, 60 h or 66 h de pending on th e ac cumulator an d fag co nditions. on ly th e c fag may be af fected by th is in struction wh ich in dicates th at i f th e or iginal bc d su m i s g reater th an 100, it all ows mul tiple pr ecision de cimal ad dition. operation [m] ac c + 0 0h o r [m] ac c + 06h or [m] ac c + 6 0h or [m] ac c + 6 6h affected fag(s) c dec [m] decrement da ta memor y description data in th e sp ecifed da ta me mory is dec remented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement da ta memor y wit h re sult in ac c description data in th e spe cifed da ta me mory i s de cremented by 1. th e res ult i s st ored in th e accumulator. the co ntents of th e da ta me mory re main un changed. operation acc [m ] ? 1 affected fag(s) z halt enter po wer d own mo de description this in struction sto ps th e pr ogram ex ecution an d tu rns of f th e sy stem cl ock. the co ntents of the da ta me mory an d re gisters ar e re tained. the wd t an d pr escaler ar e cl eared. the po wer down fag pd f is se t an d th e wd t tim e-out fag to is cl eared. operation to 0 pdf 1 affected fag(s) to, pd f inc [m] increment da ta memor y description data in th e spe cifed da ta me mory i s in cremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memor y wit h re sult in ac c description data in th e spe cifed da ta me mory is in cremented by 1. the res ult is sto red in th e ac cumulator. the co ntents of th e da ta me mory re main un changed. operation acc [m ] + 1 affected fag(s) z
rev. 1.10 186 ??ne 10? ?01? rev. 1.10 187 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi jmp addr jump unconditionally description the co ntents of th e pro gram co unter are rep laced wi th th e spe cifed add ress. pro gram execution th en co ntinues fro m th is ne w add ress. as th is req uires th e in sertion of a du mmy instruction wh ile th e ne w add ress i s l oaded, i t i s a tw o cy cle in struction. operation program c ounter ad dr affected fag(s) none mov a,[m] move da ta memor y to ac c description the co ntents of th e sp ecifed da ta me mory ar e co pied to th e ac cumulator. operation acc [m ] affected fag(s) none mov a,x move immediate d ata to ac c description the imm ediate da ta sp ecifed is lo aded in to th e ac cumulator. operation acc x affected fag(s) none mov [m],a move ac c to da ta me mory description the co ntents of th e ac cumulator ar e co pied to th e sp ecifed da ta me mory. operation [m] ac c affected fag(s) none nop no op eration description no op eration is pe rformed. ex ecution con tinues wi th th e ne xt in struction. operation no o peration affected fag(s) none or a,[m] logical or da ta me mory to ac c description data in th e ac cumulator an d th e sp ecifed da ta me mory pe rform a bit wise logical or ope ration. th e res ult i s st ored in th e ac cumulator. operation acc ac c o r [m ] affected fag(s) z or a,x logical o r imm ediate d ata to ac c description data in th e ac cumulator an d th e sp ecifed imm ediate da ta pe rform a bit wise lo gical or operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c o r x affected fag(s) z orm a,[m] logical o r ac c to da ta me mory description data in th e sp ecifed da ta me mory an d th e ac cumulator pe rform a bit wise lo gical or operation. th e res ult i s st ored in th e da ta me mory. operation [m] ac c o r [m] affected fag(s) z ret return f rom su broutine description the pro gram co unter i s res tored fro m th e st ack. pro gram ex ecution co ntinues at th e res tored a dd ress. operation program c ounter st ack affected fag(s) none
rev. 1.10 188 ?? ne 10 ? ? 01 ? rev. 1.10 189 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi ret a,x return fr om sub routine a nd lo ad imm ediate d ata to ac c description the pr ogram cou nter is re stored fr om th e sta ck an d th e ac cumulator lo aded wit h th e sp ecifed immediate da ta. pr ogram ex ecution co ntinues at th e re stored ad dress. operation program c ounter st ack acc x affected fag(s) none reti return f rom in terrupt description the pro gram co unter i s res tored fro m th e st ack an d th e in terrupts are re- enabled by se tting th e emi bit . em i is th e ma ster in terrupt gl obal en able bit . if an in terrupt wa s pe nding wh en th e reti in struction i s ex ecuted, th e pe nding int errupt rou tine wi ll be pro cessed be fore ret urning to th e ma in pro gram. operation program c ounter st ack emi 1 affected fag(s) none rl [m] rotate da ta memor y le ft description the co ntents of th e sp ecifed da ta me mory ar e ro tated le ft by 1 bit wit h bit 7 ro tated in to bit 0. operation [m].(i+1) [m ].i; ( i = 0~ 6) [m].0 [m] .7 affected fag(s) none rla [m] rotate data me mory l eft wi th res ult in ac c description the co ntents of th e sp ecifed da ta me mory ar e ro tated le ft by 1 bit wit h bit 7 ro tated in to bit 0. the ro tated re sult is sto red in th e ac cumulator an d th e co ntents of th e da ta me mory re main u ncha nged. operation acc.(i+1) [m ].i; ( i = 0~ 6) acc.0 [m ].7 affected fag(s) none rlc [m] rotate data me mory le ft th rough c arry description the co ntents of th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated le ft by 1 bit . bit 7 replaces th e ca rry bit an d th e or iginal ca rry fag is ro tated in to bit 0. operation [m].(i+1) [m ].i; ( i = 0~ 6) [m].0 c c [m] .7 affected fag(s) c rlca [m] rotate da ta me mory l eft th rough ca rry wi th res ult in ac c description data in th e sp ecifed da ta me mory a nd th e c arry fa g a re ro tated le ft by 1 bit . bit 7 re places th e carry bit an d th e or iginal ca rry fag is ro tated in to th e bit 0. the ro tated re sult is sto red in th e accumulator an d th e co ntents of th e da ta me mory re main un changed. operation acc.(i+1) [m ].i; ( i = 0~ 6) acc.0 c c [m] .7 affected fag(s) c rr [m] rotate data memor y ri ght description the c ontents o f th e sp ecifed da ta me mory a re ro tated ri ght by 1 bit wit h bit 0 ro tated in to bit 7. operation [m].i [m] .(i+1); (i = 0~ 6) [m].7 [m] .0 affected fag(s) none
rev. 1.10 188 ??ne 10? ?01? rev. 1.10 189 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi rra [m] rotate data me mory r ight w ith r esult in ac c description data in th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated ri ght by 1 bit wit h bit 0 rotated in to bit 7. the ro tated re sult is sto red in th e ac cumulator an d th e co ntents of th e data memor y rema in uncha nged. operation acc.i [m ].(i+1); ( i = 0~ 6) acc.7 [m ].0 affected fag(s) none rrc [m] rotate data me mory ri ght th rough c arry description the co ntents of th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated ri ght by 1 bit . bit 0 replaces th e ca rry bit an d th e or iginal ca rry fag is ro tated in to bit 7. operation [m].i [m] .(i+1); (i = 0~ 6) [m].7 c c [m] .0 affected fag(s) c rrca [m] rotate da ta me mory r ight thr ough ca rry w ith r esult in ac c description data in th e sp ecifed da ta me mory an d th e ca rry fag ar e ro tated ri ght by 1 bit . bit 0 re places the ca rry bit an d th e or iginal ca rry fag is ro tated in to bit 7. the ro tated re sult is sto red in th e accumulator an d th e co ntents of th e da ta me mory re main un changed. operation acc.i [m ].(i+1); ( i = 0~ 6) acc.7 c c [m] .0 affected fag(s) c sbc a,[m] subtract da ta memor y f rom ac c wit h ca rry description the co ntents of th e sp ecifed da ta me mory an d th e co mplement of th e ca rry fag ar e subtracted fro m th e ac cumulator. th e res ult i s st ored in th e ac cumulator. no te th at i f th e result of su btraction i s ne gative, th e c fa g wi ll be cl eared to 0, ot herwise i f th e res ult i s positive or ze ro, th e c fag wi ll be se t to 1. operation acc ac c ? [m ] ? c affected fag(s) ov, z, ac , c sbcm a,[m] subtract da ta memor y f rom ac c wit h ca rry and re sult in da ta memor y description the co ntents of th e sp ecifed da ta me mory an d th e co mplement of th e ca rry fag ar e subtracted fro m th e ac cumulator. th e res ult i s st ored in th e da ta me mory. no te th at i f th e result of su btraction i s ne gative, th e c fa g wi ll be cl eared to 0, ot herwise i f th e res ult i s positive or ze ro, th e c fag wi ll be se t to 1. operation [m] ac c ? [m] ? c affected fag(s) ov, z, ac , c sdz [m] skip if de crement da ta me mory is 0 description the co ntents of th e sp ecifed da ta me mory ar e frs t de cremented by 1. if th e re sult is 0 th e following in struction i s sk ipped. as th is req uires th e in sertion of a du mmy in struction wh ile the ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e pro gram proceeds wi th th e fo llowing in struction. operation [m] [m] ? 1 skip if [m ] = 0 affected fag(s) none
rev. 1.10 190 ?? ne 10 ? ? 01 ? rev. 1.10 191 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi sdza [m] skip if de crement da ta me mory is zer o wit h re sult in ac c description the co ntents of th e sp ecifed da ta me mory ar e frs t de cremented by 1. if th e re sult is 0, th e following in struction i s sk ipped. th e res ult i s st ored in th e ac cumulator bu t th e spe cifed data me mory co ntents re main un changed. as th is re quires th e in sertion of a d ummy instruction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e re sult i s no t 0, the pro gram pro ceeds wi th th e fo llowing in struction. operation acc [m ] ? 1 skip if ac c = 0 affected fag(s) none set [m] set da ta memor y description each bi t of th e sp ecifed da ta memor y is set to 1. operation [m] ff h affected fag(s) none set [m].i set bit of data memor y description bit i of th e sp ecifed da ta memor y is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment da ta memor y is 0 description the co ntents of th e spe cifed da ta me mory are fr st in cremented by 1. if th e res ult i s 0, th e following in struction i s sk ipped. as th is req uires th e in sertion of a du mmy in struction wh ile the ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e pro gram proceeds wi th th e fo llowing in struction. operation [m] [m] + 1 skip if [m ] = 0 affected fag(s) none siza [m] skip i f in crement da ta me mory i s ze ro wi th res ult in ac c description the co ntents of th e spe cifed da ta me mory are fr st in cremented by 1. if th e res ult i s 0, th e following in struction i s sk ipped. th e res ult i s st ored in th e ac cumulator bu t th e spe cifed data me mory co ntents re main un changed. as th is re quires th e in sertion of a d ummy instruction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e pro gram pro ceeds wi th th e fo llowing in struction. operation acc [m ] + 1 skip if ac c = 0 affected fag(s) none snz [m].i skip if bit i o f da ta me mory is no t 0 description if bi t i of th e spe cifed da ta me mory i s no t 0, th e fo llowing in struction i s sk ipped. as th is requires th e in sertion of a du mmy in struction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cycle in struction. if th e res ult i s 0 th e pro gram pro ceeds wi th th e fo llowing in struction. operation skip if [m ].i 0 affected fag(s) none sub a,[m] subtract da ta memor y f rom ac c description the sp ecifed da ta me mory is su btracted fr om th e co ntents of th e ac cumulator. the re sult is stored in th e ac cumulator. no te th at i f th e res ult of su btraction i s ne gative, th e c fa g wi ll be cleared to 0, ot herwise if th e re sult is po sitive or ze ro, th e c fag wi ll be se t to 1. operation acc ac c ? [m ] affected fag(s) ov, z, ac , c
rev. 1.10 190 ??ne 10? ?01? rev. 1.10 191 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi subm a,[m] subtract da ta memor y f rom ac c wit h re sult in da ta memor y description the sp ecifed da ta me mory is su btracted fr om th e co ntents of th e ac cumulator. the re sult is stored in th e da ta me mory. no te th at i f th e res ult of su btraction i s ne gative, th e c fa g wi ll be cleared to 0, ot herwise if th e re sult is po sitive or ze ro, th e c fag wi ll be se t to 1. operation [m] ac c ? [m] affected fag(s) ov, z, ac , c sub a,x subtract immediate d ata fr om ac c description the imm ediate da ta sp ecifed by th e co de is su btracted fr om th e co ntents of th e ac cumulator. the res ult i s st ored in th e ac cumulator. no te th at i f th e res ult of su btraction i s ne gative, th e c fag wi ll be cl eared to 0, ot herwise if th e re sult is po sitive or ze ro, th e c fag wi ll be se t to 1. operation acc ac c ? x affected fag(s) ov, z, ac , c swap [m] swap nibbles o f da ta me mory description the lo w-order an d hi gh-order ni bbles of th e sp ecifed da ta me mory ar e in terchanged. operation [m].3~[m].0 ? [m] .7 ~ [m] .4 affected fag(s) none swapa [m] swap nib bles o f da ta me mory wit h re sult in ac c description the lo w-order an d hi gh-order ni bbles of th e sp ecifed da ta me mory ar e in terchanged. the result is sto red in th e ac cumulator. the co ntents of th e da ta me mory re main un changed. operation acc.3 ~ ac c.0 [m] .7 ~ [m] .4 acc.7 ~ ac c.4 [m] .3 ~ [m] .0 affected fag(s) none sz [m] skip if data me mory is 0 description if th e c ontents o f th e sp ecifed da ta me mory is 0 , th e f ollowing in struction is sk ipped. as thi s requires th e in sertion of a du mmy in struction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cycle in struction. if th e res ult i s no t 0 th e pro gram pro ceeds wi th th e fo llowing in struction. operation skip if [m ] = 0 affected fag(s) none sza [m] skip if data me mory is 0 wit h d ata mo vement to ac c description the co ntents of th e sp ecifed da ta me mory ar e co pied to th e ac cumulator. if th e val ue is ze ro, the fo llowing in struction i s sk ipped. as th is req uires th e in sertion of a du mmy in struction while th e ne xt in struction i s fe tched, i t i s a tw o cy cle in struction. if th e res ult i s no t 0 th e program pro ceeds wi th th e fo llowing in struction. operation acc [m ] skip if [m ] = 0 affected fag(s) none sz [m].i skip if bit i o f da ta me mory is 0 description if bi t i of th e spe cifed da ta me mory i s 0, th e fo llowing in struction i s sk ipped. as th is req uires the in sertion of a du mmy in struction wh ile th e ne xt in struction i s fe tched, i t i s a tw o cy cle instruction. if th e res ult i s no t 0, th e pro gram pro ceeds wi th th e fo llowing in struction. operation skip if [m ].i = 0 affected fag(s) none
rev. 1.10 19 ? ?? ne 10 ? ? 01 ? rev. 1.10 19? ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi tabrd [m] read tab le to tb lh an d da ta me mory description the low by te of th e pro gram co de add ressed by th e ta ble po inter (t blp/tbhp) i s moved to th e sp ecifed da ta memor y an d th e hi gh byt e mov ed to tb lh. operation [m] pro gram co de ( low byt e) tblh pro gram co de ( high byt e) affected fag(s) none tabrdl [m] read table ( last pa ge) to tb lh and da ta memor y description the low by te of th e pro gram co de (l ast pa ge) add ressed by th e ta ble po inter (t blp/tbhp) i s moved to th e sp ecifed da ta memor y an d th e hi gh byt e mov ed to tb lh. operation [m] pro gram co de ( low byt e) tblh pro gram co de ( high byt e) affected fag(s) none xor a,[m] logical xo r da ta me mory to ac c description data in th e ac cumulator an d th e sp ecifed da ta me mory pe rform a bit wise lo gical xo r operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c xo r [m ] affected fag(s) z xorm a,[m] logical xo r ac c to da ta me mory description data in th e sp ecifed da ta me mory an d th e ac cumulator pe rform a bit wise lo gical xo r operation. th e res ult i s st ored in th e da ta me mory. operation [m] ac c x or [m] affected fag(s) z xor a,x logical xor imm ediate d ata to ac c description data in th e ac cumulator an d th e sp ecifed imm ediate da ta pe rform a bit wise lo gical xo r operation. th e res ult i s st ored in th e ac cumulator. operation acc ac c xo r x affected fag(s) z
rev. 1.10 19? ??ne 10? ?01? rev. 1.10 19 ? ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supp lementary i nformation wi th r egard t o pac kaging i s l isted be low. cl ick o n t he r elevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information ? pb free products ? green packages products
rev. 1.10 194 ?? ne 10 ? ? 01 ? rev. 1.10 195 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.158 c 0.008 0.01 ? c' 0. ?? 5 0. ? 47 d 0.049 0.065 e 0.0 ? 5 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 0o 8o symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 4.01 c 0. ? 0 0. ? 0 c' 8.51 8.81 d 1. ? 4 1.65 e 0.64 f 0.10 0. ? 5 g 0. ? 8 1. ? 7 h 0.18 0. ? 5 0o 8o
rev. 1.10 194 ??ne 10? ?01? rev. 1.10 195 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c' 0. ?? 5 0. ? 46 d 0.054 0.060 e 0.0 ? 5 f 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 0o 8o symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c' 8.51 8.79 d 1. ? 7 1.5 ? e 0.64 f 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 0o 8o
rev. 1.10 196 ?? ne 10 ? ? 01 ? rev. 1.10 197 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.157 c 0.008 0.01 ? c' 0. ? 86 0. ? 94 d 0.054 0.060 e 0.0 ? 5 f 0.004 0.010 g 0.0 ?? 0.0 ? 8 h 0.007 0.010 0o 8o symbol dimensions in mm min. nom. max. a 5.79 6. ? 0 b ? .81 ? .99 c 0. ? 0 0. ? 0 c' 9.80 10.01 d 1. ? 7 1.5 ? e 0.64 f 0.10 0. ? 5 g 0.56 0.71 h 0.18 0. ? 5 0o 8o
rev. 1.10 196 ??ne 10? ?01? rev. 1.10 197 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi saw type 20-pin (4mm 4 mm) qfn outline dimensions gtk symbol dimensions in inch min. nom. max. a 0.0 ? 1 0.0 ? 5 a1 0.000 0.001 0.00 ? a ? 0.008 b 0.007 0.010 0.01 ? d 0.157 e 0.157 e 0.0 ? 0 d ? 0.075 0.081 e ? 0.075 0.081 l 0.01 ? 0.016 0.0 ? 0 k 0.008 symbol dimensions in mm min. nom. max. a 0.80 0.90 a1 0.00 0.0 ? 0.05 a ? 0. ? 0 ? b 0.18 0. ? 5 0. ? 0 d 4.00 e 4.00 e 0.50 d ? 1.90 ? .00 ? .05 e ? 1.90 ? .00 ? .05 l 0. ? 0 0.40 0.50 k 0. ? 0
rev. 1.10 198 ?? ne 10 ? ? 01 ? rev. 1.10 199 ??ne 10? ?01? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi 48-pin lqfn (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 50 0. ? 58 b 0. ? 7 ? 0. ? 80 c 0. ? 50 0. ? 58 d 0. ? 7 ? 0. ? 80 e 0.0 ? 0 f 0.008 g 0.05 ? 0.057 h 0.06 ? i 0.004 ? 0.018 0.0 ? 0 k 0.004 0.008 0o 7o symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 5.00 f 0. ? 0 g 1. ? 5 1.45 h 1.60 i 0.10 ? 0.45 0.75 k 0.10 0. ? 0 0o 7o
rev. 1.10 198 ??ne 10? ?01? rev. 1.10 199 ?? ne 10 ? ? 01 ? HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi HT68FB540/ht68fb550/ht68fb560 i/o flash usb 8-bit mcu with spi copyright ? ? 01 ? by holtek semiconductor inc. the information appearing in this data sheet is believed to be acc ? rate at the time of p ? blication. however ? holtek ass ? mes no responsibility arising from the ? se of the specifcations described. the applications mentioned herein are used solely for the p ? rpose of ill ? stration and holtek makes no warranty or representation that s ? c h applications will be s ? it able witho ? t f ? r ther modification ? nor r ecommends the ? se of its prod ? cts for application that may present a risk to h ? man life d ? e to malf ? nction or otherwise. holtek's prod ? cts are not a ? thorized for ? se as critical components in life s ? pport devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit o ? r web site at http://www.holtek.com .

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